UGC NET Computer Science Computer System Architecture Previous Year Questions (PYQs)

All 133 Computer System Architecture PYQs

Ordered newest exam first. Each question links back to the full paper it came from.

1. Question 1

   UGC NET June 2026

   What does Amdahl's Law describe in the context of parallel processing?

   1. AMaximum speedup achievable, considering serial and parallel portions of a program
   2. BEfficiency of message passing in a distributed-memory system
   3. CComputational efficiency of a parallel algorithm
   4. DReliability of a fault-tolerant system

   Answer: (A) Maximum speedup achievable, considering serial and parallel portions of a program

   Explanation

   Amdahl's Law bounds the speedup obtainable by parallelisation using the fraction that remains serial. Even infinitely fast parallel work cannot remove the serial bottleneck.

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2. Question 2

   UGC NET June 2026

   Arrange the following in terms of capacity from smallest to largest.

   A. L3 cache
   B. L1 cache
   C. CPU register
   D. L2 cache

   1. AC, D, B, A
   2. BC, A, B, D
   3. CC, B, D, A
   4. DA, C, D, B

   Answer: (C) C, B, D, A

   Explanation

   Registers are the smallest storage locations, followed by L1 cache, then L2 cache, and then the larger L3 cache. Thus the increasing-capacity sequence is C, B, D, A.

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3. Question 3

   UGC NET June 2026

   For sending input I₆ to the output line of an 8×1 multiplexer, which selection-line combination is required?

   1. A001
   2. B100
   3. C110
   4. D111

   Answer: (C) 110

   Explanation

   An 8-to-1 multiplexer uses three select bits to encode the input index in binary. Since 6 in binary is 110, the select lines S₂S₁S₀ must be 110; 111 would instead select I₇.

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4. Question 4

   UGC NET June 2026

   The term "double buffered" is used in which of the following?

   1. ASynchronous communication interface
   2. BAsynchronous communication interface
   3. CAddressing mode
   4. DSerial communication

   Answer: (B) Asynchronous communication interface

   Explanation

   Double buffering permits one buffer to be filled while another is consumed, helping asynchronous producer and consumer rates operate smoothly. It is not an addressing mode, and serial communication by itself does not define double buffering.

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5. Question 5

   UGC NET June 2026

   The combination of selection lines for sending input I₁₄ to the output in the shown 64 × 1 multiplexer is:

   

   64 × 1 multiplexer selection-line diagram.

   1. A001111
   2. B110000
   3. C111100
   4. D001110

   Answer: (D) 001110

   Explanation

   A 64-to-1 multiplexer needs six selection bits. The binary representation of input index 14 is 001110, so S₅…S₀ must be 001110; the other choices represent input indices 15, 48, and 60.

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6. Question 6

   UGC NET June 2026

   Match List-I with List-II.

   A. FDM
   B. Digital circuits
   C. A two-variable function
   D. J-K flip-flop

   List-I	List-II
   A. FDM B. Digital circuits C. Two-variable function D. J-K flip-flop	I. Four minterms II. Frequency Division Multiplexing III. Universal flip-flop IV. Combinational or sequential

   1. AA-II, B-I, C-IV, D-III
   2. BA-II, B-IV, C-I, D-III
   3. CA-II, B-III, C-I, D-IV
   4. DA-II, B-I, C-III, D-IV

   Answer: (B) A-II, B-IV, C-I, D-III

   Explanation

   FDM means frequency-division multiplexing (II). Digital circuits may be combinational or sequential (IV), a two-variable Boolean function has four minterms (I), and the J-K flip-flop is universal (III).

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7. Question 7

   UGC NET June 2026

   Average main-memory access time is 130 ns, cache access time is 100 ns, and the cache hit ratio is 75%. What is the average time to access a word?

   1. A130 ns
   2. B150 ns
   3. C132.5 ns
   4. D107.5 ns

   Answer: (D) 107.5 ns

   Explanation

   Separate the accesses into 75 cache hits and 25 misses per 100 references. Those contribute 75 × 100 ns and 25 × 130 ns respectively, totalling 10,750 ns; dividing by 100 gives 107.5 ns. The other answers omit the hit ratio or reverse the two access times.

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8. Question 8

   UGC NET June 2026

   Which IC family has the lowest power consumption?

   1. AECL
   2. BMOS
   3. CTTL
   4. DCMOS

   Answer: (D) CMOS

   Explanation

   CMOS has very low static power consumption because its complementary transistor pair ideally draws significant current only while switching. ECL and TTL consume substantially more steady power.

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9. Question 9

   UGC NET June 2026

   Simplify F(A,B,C,D) = Σm(3,6,7,11,12,13,14,15) using a four-variable Karnaugh map.

   1. AĀB + B̄C + C̄D
   2. BĀB + C̄D + AB̄
   3. CAB + BC + CD
   4. DCD + AC̄ + BD

   Answer: (C) AB + BC + CD

   Explanation

   The four adjacent cells m12, m13, m14, and m15 form the product AB. The cells m6, m7, m14, and m15 form BC. The cells m3, m7, m11, and m15 form CD. Evaluating AB + BC + CD therefore yields true precisely for 3, 6, 7, 11, 12, 13, 14, and 15. For example, m3 is covered by CD, m6 by BC, and m12 by AB; no product term turns on a minterm outside the stated set. Hence option C is the minimal correct form.

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10. Question 10

    UGC NET June 2026

    What is memory interleaving?

    1. ALayering memory stacks one above another
    2. BA hierarchy of different memory types
    3. CDividing memory into modules so the CPU can access multiple modules simultaneously
    4. DCombining different memory types

    Answer: (C) Dividing memory into modules so the CPU can access multiple modules simultaneously

    Explanation

    Interleaved memory distributes consecutive addresses across independent memory modules. While one module completes an access, another can begin the next, improving throughput through overlapping accesses.

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11. Question 11

    UGC NET June 2026

    In the given program, 1% of the code accounts for 50% of execution time. What percentage decrease in execution time results from rewriting that 1% in assembly language, which runs five times faster?

    1. A20%
    2. B32%
    3. C40%
    4. D60%

    Answer: (C) 40%

    Explanation

    Treat the original runtime as 100 units. The unchanged 99% of code takes 50 units; the hot 1% originally takes 50 but after a 5× speedup takes 10. The new total is 60, so the reduction is 100 − 60 = 40%.

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12. Question 12

    UGC NET January 2026

    Arrange the following events in the correct order when an interrupt occurs during instruction execution.
    A. Save program counter (PC) and status register
    B. Fetch interrupt vector from memory
    C. Execute the interrupted instruction completely
    D. Transfer control to interrupt service routine (ISR)
    E. Restore PC and register after ISR

    1. AA, B, C, D, E
    2. BE, D, C, B, A
    3. CC, A, B, D, E
    4. DA, B, E, C, D

    Answer: (C) C, A, B, D, E

    Explanation

    An interrupt is only acted on at an instruction boundary, and the processor then follows a fixed save-dispatch-restore sequence.

    C, A, B, D, E.

    • C. Execute the interrupted instruction completely — the processor finishes the instruction already in progress before reacting to the interrupt.
    • A. Save program counter (PC) and status register — the context is saved so the interrupted program can be restored later.
    • B. Fetch interrupt vector from memory — the processor locates the address of the appropriate interrupt service routine.
    • D. Transfer control to interrupt service routine (ISR) — execution jumps to that routine.
    • E. Restore PC and register after ISR — once the ISR finishes, the saved PC and status register are restored so normal execution can resume.

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13. Question 13

    UGC NET January 2026

    Which of the following are characteristics of RISC architecture?

    A. Large instruction set with many adversing modes
    B. Fixed instruction length
    C. Emphasis on software rather than hardware
    D. Simple instruction that execute in one cycle

    1. AA, B Only
    2. BB, C, D Only
    3. CA, C, D only
    4. DA, B, C, D

    Answer: (B) B, C, D Only

    Explanation

    RISC (Reduced Instruction Set Computer) design keeps the hardware simple and pushes complexity into the compiler, which is the opposite philosophy of CISC.

    • A. Large instruction set with many adversing modes — this describes CISC, not RISC. RISC deliberately keeps the instruction set small with few addressing modes so the hardware stays simple.
    • B. Fixed instruction length — correct. RISC instructions are uniform in length so they can be fetched and decoded quickly in a pipeline.
    • C. Emphasis on software rather than hardware — correct. RISC shifts complexity to the compiler, letting the hardware stay minimal.
    • D. Simple instruction that execute in one cycle — correct. Most RISC instructions are designed to complete in a single clock cycle to support efficient pipelining.

    Only B, C and D describe RISC, so the answer is B, C, D only.

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14. Question 14

    UGC NET January 2026

    Assertion (A): Instruction pipelining improves CPU throughput.
    Reason (R): Pipelining decreases the execution time of each individual instruction.

    1. ABoth A and R are correct and R is the correct explanation of A
    2. BBoth A and R are correct but R is NOT the correct explanation of A
    3. CA is correct but R is not correct
    4. DA is not correct but R is correct

    Answer: (C) A is correct but R is not correct

    Explanation

    Pipelining overlaps the execution stages of multiple instructions so that a new instruction can start before the previous one finishes, which increases the number of instructions completed per unit time. This is throughput.

    Assertion A is correct because this overlap is exactly why pipelining improves throughput.

    Reason R claims pipelining decreases the execution time of each individual instruction, but this is false. Each instruction still takes roughly the same number of pipeline stages to complete, sometimes even more due to hazards and stalls. Pipelining does not make any single instruction finish faster — it only allows more instructions to be in flight at the same time.

    Since A is true and R is false, the correct choice is that A is correct but R is not correct.

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15. Question 15

    UGC NET January 2026

    Based on the passage, how much CPU time is consumed by programmed I/O?

    A system transfers data blocks of 2000 bytes.

    With programmed I/O, each byte transfer takes 6 CPU cycles.
    With direct memory access (DMA), the block transfer takes 3000 cycles in total for the DMA controller, in addition to a CPU setup overhead of 200 cycles.
    The CPU clock speed is 1 GHz, so one clock cycle equals 1 nanosecond.

    1. A12 μs
    2. B20 μs
    3. C24 μs
    4. D30 μs

    Answer: (A) 12 μs

    Explanation

    Programmed I/O keeps the CPU busy for every single byte of the transfer, so the total CPU cycles must be computed first and then converted to time using the clock speed.

    CPU cycles = 2000 bytes × 6 cycles/byte = 12,000 cycles
    CPU time = 12,000 cycles / 1 GHz = 12,000 nanoseconds = 12 microseconds

    12 microseconds is the CPU time consumed by programmed I/O.

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16. Question 16

    UGC NET January 2026

    Based on the passage, which approach is more CPU-efficient for large block transfers?

    A system transfers data blocks of 2000 bytes.

    With programmed I/O, each byte transfer takes 6 CPU cycles.
    With direct memory access (DMA), the block transfer takes 3000 cycles in total for the DMA controller, in addition to a CPU setup overhead of 200 cycles.
    The CPU clock speed is 1 GHz, so one clock cycle equals 1 nanosecond.

    1. AProgrammed I/O
    2. BDMA
    3. CBoth programmed I/O and DMA
    4. DDepends on block size

    Answer: (B) DMA

    Explanation

    DMA is designed to free the CPU from handling each byte of a transfer individually. The DMA controller moves the entire block on its own, and the CPU only pays a brief 200-cycle setup cost, compared with 12,000 cycles of CPU involvement under programmed I/O for the same 2000-byte block.

    Because the CPU is occupied for far fewer cycles with DMA, DMA is the more CPU-efficient approach for large block transfers.

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17. Question 17

    UGC NET January 2026

    Based on the passage, how many CPU cycles are spent with DMA?

    A system transfers data blocks of 2000 bytes.

    With programmed I/O, each byte transfer takes 6 CPU cycles.
    With direct memory access (DMA), the block transfer takes 3000 cycles in total for the DMA controller, in addition to a CPU setup overhead of 200 cycles.
    The CPU clock speed is 1 GHz, so one clock cycle equals 1 nanosecond.

    1. A200 Cycles
    2. B3000 Cycles
    3. C3200 Cycles
    4. D4000 Cycles

    Answer: (A) 200 Cycles

    Explanation

    With DMA, the CPU only performs the initial setup work and then hands off the actual byte-by-byte transfer to the DMA controller entirely. The 3000 cycles described for the block transfer are the DMA controller's own bus cycles for moving the data, not CPU cycles, so they do not count against the CPU's workload.

    CPU cycles spent with DMA = 200 cycles (setup overhead only)

    The CPU is occupied for only the 200-cycle setup overhead while DMA handles the transfer.

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18. Question 18

    UGC NET January 2026

    Based on the passage, how many CPU cycles are spent using programmed I/O?

    A system transfers data blocks of 2000 bytes.

    With programmed I/O, each byte transfer takes 6 CPU cycles.
    With direct memory access (DMA), the block transfer takes 3000 cycles in total for the DMA controller, in addition to a CPU setup overhead of 200 cycles.
    The CPU clock speed is 1 GHz, so one clock cycle equals 1 nanosecond.

    1. A2000
    2. B6000
    3. C12000
    4. D20000

    Answer: (C) 12000

    Explanation

    Under programmed I/O, the CPU itself executes the transfer of every byte, at a fixed cost per byte given in the passage.

    CPU cycles = 2000 bytes × 6 cycles/byte = 12,000 cycles

    12,000 cycles is the total CPU cycle cost of transferring the block with programmed I/O.

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19. Question 19

    UGC NET January 2026

    Based on the passage, how much CPU time is consumed by DMA overhead?

    A system transfers data blocks of 2000 bytes.

    With programmed I/O, each byte transfer takes 6 CPU cycles.
    With direct memory access (DMA), the block transfer takes 3000 cycles in total for the DMA controller, in addition to a CPU setup overhead of 200 cycles.
    The CPU clock speed is 1 GHz, so one clock cycle equals 1 nanosecond.

    1. A0.2 μs
    2. B2.0 μs
    3. C3.0 μs
    4. D12.0 μs

    Answer: (A) 0.2 μs

    Explanation

    The CPU's only involvement in a DMA transfer is the setup overhead, so that overhead in cycles converts directly to time using the 1 GHz clock.

    CPU time = 200 cycles / 1 GHz = 200 nanoseconds = 0.2 microseconds

    0.2 microseconds is the CPU time consumed by DMA overhead.

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20. Question 20

    UGC NET June 2025

    What is the binary equivalent of (A0F)₁₆?

    1. A111000111
    2. B101001111
    3. C101000001111
    4. D111100001010

    Answer: (C) 101000001111

    Explanation

    Convert each hexadecimal digit to four bits: A = 1010, 0 = 0000, and F = 1111. Concatenating them gives 101000001111.

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21. Question 21

    UGC NET June 2025

    In an I/O operation, what does a write operation do?

    1. ATransfers data from an I/O device to memory
    2. BTransfers data from memory to an I/O device
    3. CTransfers data from a CPU register to memory
    4. DTransfers data from a CPU register to an I/O device

    Answer: (B) Transfers data from memory to an I/O device

    Explanation

    A write operation sends data outward from the computer's memory to a peripheral or I/O device. The opposite direction, from a device into memory, is a read operation.

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22. Question 22

    UGC NET June 2025

    The transformation of data from main memory to cache memory is called:

    1. AData exchange
    2. BData transformation
    3. CMapping
    4. DMatching

    Answer: (C) Mapping

    Explanation

    A cache uses a mapping scheme—such as direct, associative, or set-associative mapping—to determine where a main-memory block is placed in cache.

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23. Question 23

    UGC NET June 2025

    What is the Gray-code equivalent of decimal 8?

    1. A1000
    2. B1100
    3. C1010
    4. D1110

    Answer: (B) 1100

    Explanation

    Decimal 8 is binary 1000. Gray code is found by XORing the binary number with itself shifted right one bit: 1000 XOR 0100 = 1100.

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24. Question 24

    UGC NET June 2025

    A computer processes an instruction by fetching it, decoding it, calculating its effective address, fetching operands, and executing it. Which sequence is correct?

    1. AA, B, C, D, E
    2. BB, A, D, A, E
    3. CB, C, A, D, E
    4. DC, B, A, D, E

    Answer: (C) B, C, A, D, E

    Explanation

    The processor must first fetch the instruction and decode it to know its addressing mode. It can then calculate the effective address, fetch the needed operands, and execute the operation. That order is B, C, A, D, E.

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25. Question 25

    UGC NET June 2025

    In an arithmetic pipeline, the operations are compare exponents, align mantissas, add or subtract mantissas, and normalize the result. Which sequence is correct?

    1. AD, A, B, C
    2. BD, B, A, C
    3. CB, C, A, D
    4. DB, C, D, A

    Answer: (A) D, A, B, C

    Explanation

    Floating-point operands must first have their exponents compared so the smaller mantissa can be aligned. After alignment, the mantissas are added or subtracted, and the resulting normalized form is produced last.

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26. Practise Computer System Architecture in a timed set

27. Question 26

    UGC NET June 2025

    To input data through a CPU-controlled I/O program, the actions are reading the status register, checking its flag bit, reading the data register, and transferring data to memory. Which sequence is correct?

    1. AA, B, C, D
    2. BB, A, C, D
    3. CC, B, A, D
    4. DA, C, B, D

    Answer: (A) A, B, C, D

    Explanation

    The program first reads the device status, then tests the readiness flag. Only after the flag indicates data is available should it read the data register and transfer that value into memory. Thus the sequence is A, B, C, D.

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28. Question 27

    UGC NET June 2025

    Which statements are true: write-through updates only cache; write-back updates cache and main memory together; private writable caches create coherence problems; and cache coherence can be solved by a hardware-only scheme?

    1. AA and B only
    2. BB and C only
    3. CC and D only
    4. DA, B, and C only

    Answer: (C) C and D only

    Explanation

    Write-through updates cache and main memory on each write, so A is false. Write-back normally updates main memory later, on eviction, so B is false. Private writable caches do create coherence issues, and hardware protocols such as snooping or directory mechanisms can solve them; C and D are true.

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29. Question 28

    UGC NET June 2025

    Which gate does not output 1 when both inputs are 0?

    1. ANAND and NOR only
    2. BNOR and XOR only
    3. CXOR and XNOR only
    4. DXOR only

    Answer: (D) XOR only

    Explanation

    At inputs 0 and 0, NAND outputs 1, NOR outputs 1, and XNOR outputs 1 because the inputs match. XOR alone outputs 0, so it is the only listed gate that does not output 1.

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30. Question 29

    UGC NET June 2025

    Match address space, memory space, cache memory, and segmented program with associative mapping, logical address, physical address, and virtual address.

    List I	List II
    A. Address Space	I. Associative Mapping
    B. Memory Space	II. Logical address
    C. Cache Memory	III. Physical address
    D. Segmented Program	IV. Virtual address

    1. AA-IV, B-III, C-I, D-II
    2. BA-I, B-II, C-IV, D-III
    3. CA-III, B-IV, C-I, D-II
    4. DA-II, B-IV, C-I, D-III

    Answer: (A) A-IV, B-III, C-I, D-II

    Explanation

    Address space is the virtual address range visible to a process, whereas memory space is physical memory. Cache memory uses associative mapping, and a segmented program's segment-plus-offset form is a logical address. The matching A-IV, B-III, C-I, D-II is option A.

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31. Question 30

    UGC NET January 2025

    Give the correct order of the instruction cycle:

    A. Read the effective address
    B. Fetch the instruction
    C. Execute the instruction
    D. Decode the instruction

    1. AA, B, C, D
    2. BB, D, A, C
    3. CB, A, D, C
    4. DA, B, D, C

    Answer: (B) B, D, A, C

    Explanation

    A processor fetches an instruction, decodes it, obtains the effective address where needed, and executes it. Therefore B, D, A, C is correct. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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32. Question 31

    UGC NET January 2025

    Which of the following do not represent memory-reference instructions?

    A. LDA (Load Accumulator)
    B. CMA (Complement Accumulator)
    C. STA (Store Accumulator)
    D. INP (Input Character)
    E. ADD (Add to Accumulator)

    1. AB and C only
    2. BB and D only
    3. CA and D only
    4. DA and E only

    Answer: (B) B and D only

    Explanation

    In the basic computer instruction set, a memory-reference instruction takes its operand from memory: LDA (load AC from memory), STA (store AC to memory) and ADD (add a memory word to AC) — statements A, C and E. CMA (complement AC) is a register-reference instruction and INP (input a character into AC) is an input-output instruction; neither one accesses memory. The instructions that are not memory-reference are therefore B and D, which is option B.

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33. Question 32

    UGC NET January 2025

    Match List-I with List-II.

    List-I	List-II
    A. (11011)₂ B. Complements C. Parity bits D. Variable-length instruction	I. Error-detection code II. CISC III. Negative number IV. (33)₁₆

    1. AA-IV, B-I, C-III, D-II
    2. BA-IV, B-III, C-I, D-II
    3. CA-IV, B-II, C-III, D-I
    4. DA-I, B-IV, C-II, D-III

    Answer: (B) A-IV, B-III, C-I, D-II

    Explanation

    (11011)₂ equals (33)₁₆; complements represent negative numbers; parity bits are error-detection codes; and variable-length instructions are characteristic of CISC. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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34. Question 33

    UGC NET January 2025

    A pipeline multiplier uses two carry-save adders (CSAs) and a carry-propagate adder (CPA). Arrange the following stages in the proper order.

    A. Two CSAs merge four numbers into two numbers.
    B. A CPA adds two numbers.
    C. Two levels of four CSAs are used.
    D. Eight partial products are generated.

    1. AA, C, B, D
    2. BD, C, A, B
    3. CB, D, C, A
    4. DA, C, D, B

    Answer: (B) D, C, A, B

    Explanation

    A multiplier first generates partial products, reduces them through carry-save-adder levels, compresses the final four values to two, and uses a carry-propagate adder last. Hence D, C, A, B.

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35. Question 34

    UGC NET January 2025

    Which of the following are not data-manipulation instructions?

    A. Call
    B. Load
    C. And
    D. Increment
    E. Shift

    1. AC and E only
    2. BA and B only
    3. CD and E only
    4. DA and C only

    Answer: (B) A and B only

    Explanation

    The official answer key selects Call and Load. The item uses “data-manipulation instructions” in its particular instruction-set classification, distinguishing control/transfer and load operations from arithmetic/logical manipulation.

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36. Question 35

    UGC NET January 2025

    Arrange the following in increasing order of access time.

    A. Solid-state drive
    B. Optical disks
    C. DRAM
    D. SRAM
    E. Registers

    1. AD, C, A, B, E
    2. BB, D, C, A, E
    3. CA, E, B, D, C
    4. DE, D, C, A, B

    Answer: (D) E, D, C, A, B

    Explanation

    Registers are fastest, followed by SRAM, DRAM, SSD and optical disk. Thus increasing access time is E, D, C, A, B. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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37. Question 36

    UGC NET January 2025

    Which table for a dynamic pipeline becomes more interesting when a nonlinear pattern follows?

    1. AReservation table
    2. BConfusion table
    3. CInverted table
    4. DGreedy table

    Answer: (A) Reservation table

    Explanation

    A reservation table records stage use over time. It is the standard representation for analysing collision constraints and nonlinear patterns in dynamic pipelines. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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38. Question 37

    UGC NET January 2025

    Which is often needed to evaluate cache performance?

    1. AHit ratio
    2. BLatency
    3. CCache traces
    4. DTransfer rate

    Answer: (A) Hit ratio

    Explanation

    The hit ratio is the basic measure of how often cache accesses are satisfied by the cache rather than a slower lower memory level. The correct option follows from the stated definition or calculation; the other options omit a necessary condition or describe a different concept.

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39. Question 38

    UGC NET August 2024

    Consider the following relations on {1, 2, 3, 4}. Which of the following relations are reflexive?

    A. R₁ = {(1,1),(1,2),(2,1),(2,2),(3,4),(4,1),(4,4)}
    B. R₂ = {(1,1),(1,2),(2,1)}
    C. R₃ = {(1,1),(1,2),(1,4),(2,1),(2,2),(3,3),(4,1),(4,4)}
    D. R₄ = {(2,1),(3,1),(3,2),(4,1),(4,2),(4,3)}
    E. R₅ = {(1,1),(1,2),(1,3),(1,4),(2,2),(2,3),(2,4),(3,3),(3,4),(4,4)}

    1. A(A), (B) and (C) Only
    2. B(A), (D) and (E) Only
    3. C(D) and (E) Only
    4. D(C) and (E) Only

    Answer: (D) (C) and (E) Only

    Explanation

    A relation on {1, 2, 3, 4} is reflexive only if it contains all four self-pairs (1,1), (2,2), (3,3) and (4,4). R₁ omits (3,3); R₂ omits (2,2), (3,3) and (4,4); R₄ contains no self-pair at all. R₃ and R₅ each contain all four, so only (C) and (E) are reflexive — option D.

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40. Question 39

    UGC NET August 2024

    Match List-I with List-II.

    List-I (IP Address)	List-II (Class)
    (A) 10.20.30.40	(I) Class E
    (B) 210.20.30.3	(II) Class B
    (C) 180.30.100.10	(III) Class A
    (D) 252.5.15.11	(IV) Class C

    1. A(A)-(II), (B)-(III), (C)-(I), (D)-(IV)
    2. B(A)-(I), (B)-(IV), (C)-(II), (D)-(III)
    3. C(A)-(I), (B)-(II), (C)-(IV), (D)-(III)
    4. D(A)-(III), (B)-(IV), (C)-(II), (D)-(I)

    Answer: (D) (A)-(III), (B)-(IV), (C)-(II), (D)-(I)

    Explanation

    The first octet fixes the class. 10 falls in 1-126, so 10.20.30.40 is Class A and (A)-(III). 210 falls in 192-223, so 210.20.30.3 is Class C and (B)-(IV). 180 falls in 128-191, so 180.30.100.10 is Class B and (C)-(II). 252 falls in 240-255, so 252.5.15.11 is Class E and (D)-(I). Option D is correct.

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41. Question 40

    UGC NET August 2024

    Find the correct sequence of the storage devices
    in descending order based on their access time.
    A. Registers
    B. Magnetic Disk
    C. Magnetic Tapes
    D. Main memory
    E. Optical Disk

    1. A(B), (A), (D), (C), (E)
    2. B(B), (A), (E), (D), (C)
    3. C(C), (B), (A), (E), (D)
    4. D(C), (E), (B), (D), (A)

    Answer: (D) (C), (E), (B), (D), (A)

    Explanation

    Descending access time means slowest first: magnetic tape (seconds), then optical disk, then magnetic disk (milliseconds), then main memory (nanoseconds), and finally registers, which are fastest. That is (C), (E), (B), (D), (A) — option D.

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42. Question 41

    UGC NET August 2024

    A CPU has a 5-stage pipeline with the following
    stages Fetch (F), Decode (D), Execute (E), Memory
    (M) and Write-back (W). Each stage takes one
    clock cycle to complete. Assume there are no
    pipeline stalls and the pipeline is initially empty.
    How many clock cycles are required to complete
    the execution of 10 instructions?

    1. A10
    2. B14
    3. C15
    4. D19

    Answer: (B) 14

    Explanation

    A k-stage pipeline completes n instructions in k + n − 1 cycles once it has been filled. With k = 5 and n = 10 that is 5 + 10 − 1 = 14 cycles, so option B is correct.

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43. Question 42

    UGC NET August 2024

    Consider the following, where p and q are two statements.

    A. ¬(p ∧ q) ≡ ¬p ∨ ¬q
    B. ¬(p ∨ q) ≡ ¬p ∧ ¬q
    C. p ∧ ¬p ≡ T
    D. ¬(p ⇒ q) ≡ p ∧ ¬q
    E. p ∨ q ≡ ¬p ∨ ¬q

    1. A(A), (B) and (D) only
    2. B(A), (C) and (D) only
    3. C(C), (D) and (E) only
    4. D(A), (B) and (C) only

    Answer: (A) (A), (B) and (D) only

    Explanation

    By De Morgan’s laws ¬(p ∧ q) ≡ ¬p ∨ ¬q and ¬(p ∨ q) ≡ ¬p ∧ ¬q, so (A) and (B) hold. For (D), p ⇒ q is ¬p ∨ q, so ¬(p ⇒ q) ≡ ¬(¬p ∨ q) ≡ p ∧ ¬q — also true. (C) fails because p ∧ ¬p is a contradiction, not a tautology, and (E) fails on the row p = q = T. Only (A), (B) and (D) — option A.

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44. Question 43

    UGC NET August 2024

    Match List-I with List-II.

    List-I (Counter)	List-II (uses/working)
    (A) N-bit Ring Counter	(I) Uses universal clock
    (B) Synchronous Counter	(II) Counts exactly N states
    (C) Asynchronous Counter	(III) Counts 0 to 9
    (D) Decimal Counter	(IV) Main clock is applied to first flip-flop only

    1. A(A)-(II), (B)-(IV), (C)-(I), (D)-(III)
    2. B(A)-(IV), (B)-(II), (C)-(III), (D)-(I)
    3. C(A)-(II), (B)-(I), (C)-(IV), (D)-(III)
    4. D(A)-(IV), (B)-(I), (C)-(II), (D)-(III)

    Answer: (C) (A)-(II), (B)-(I), (C)-(IV), (D)-(III)

    Explanation

    An N-bit ring counter cycles through exactly N states, so (A)-(II). A synchronous counter clocks every flip-flop from one common clock, giving (B)-(I). In an asynchronous (ripple) counter only the first flip-flop sees the main clock, so (C)-(IV). A decimal counter counts 0 to 9, so (D)-(III). Option C is correct.

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45. Question 44

    UGC NET August 2024

    Consider the following statement regarding
    special purpose registers.
    A. Program Counter (PC) keeps the track of next
    instruction executed
    B. Instruction register holds the address of first
    instruction to be executed
    C. Accumulator holds the output of ALU
    D. Program Counter ( PC ) keeps the track of
    only first instruction of the program

    1. A(A) and (C) Only
    2. B(A) and (D) Only
    3. C(B) and (D) Only
    4. D(A), (B) and (C) Only

    Answer: (A) (A) and (C) Only

    Explanation

    (A) is true — the program counter holds the address of the next instruction to be executed. (C) is true — the accumulator holds the ALU’s result. (B) is false: the instruction register holds the instruction currently being executed, not an address. (D) is false: the PC tracks the next instruction throughout execution, not only the first. Only (A) and (C) — option A.

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46. Question 45

    UGC NET August 2024

    A multi processor system with 16 processors is
    used to execute a parallelizable task. If the serial
    portion of the task takes 200 clock cycles and
    the parallel portion take 800 clock cycles. When
    all 16 processor are used how many total clock
    cycles are required to complete the task ?

    1. A250
    2. B300
    3. C400
    4. D450

    Answer: (A) 250

    Explanation

    The 200-cycle serial portion cannot be sped up. The 800-cycle parallel portion divides across 16 processors, taking 800/16 = 50 cycles. The total is 200 + 50 = 250 cycles, so option A is correct.

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47. Question 46

    UGC NET August 2024

    Arrange the given steps required for a Direct
    Memory Access (DMA) transfer in the correct
    order.
    A. Initiate DMA transfer request
    B. Transfer data directly between peripheral and
    memory
    C. Processor grants DMA control over the
    system bus
    D. DMA controller completes data transfer and
    signals completion

    1. A(C), (A), (B), (D)
    2. B(A),(C),(B),(D)
    3. C(A), (B), (C), (D)
    4. D(C), (B), (A), (D)

    Answer: (B) (A),(C),(B),(D)

    Explanation

    A DMA transfer begins with the peripheral raising a transfer request (A). The processor then releases the bus and grants the controller DMA control (C). The controller moves data directly between peripheral and memory (B), and finally signals completion (D). That order is option B.

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48. Question 47

    UGC NET August 2024

    Match List-I with List-II.

    List-I (Recurrence Relation)	List-II (Complexity)
    (A) T(n) = 2T(n/2) + n	(I) T(n) = θ(n log n) {exact solution}
    (B) T(n) = T(n/2) + 1	(II) O(n²)
    (C) T(n) = 2T(n/2) + 1	(III) T(n) = θ(n) {exact solution}
    (D) T(n) = T(n−1) + n	(IV) O(n)

    1. A(A)-(I), (B)-(IV), (C)-(III), (D)-(II)
    2. B(A)-(IV), (B)-(II), (C)-(I), (D)-(III)
    3. C(A)-(I), (B)-(III), (C)-(IV), (D)-(II)
    4. D(A)-(III), (B)-(I), (C)-(IV), (D)-(II)

    Answer: (C) (A)-(I), (B)-(III), (C)-(IV), (D)-(II)

    Explanation

    By the Master Theorem, T(n) = 2T(n/2) + n is θ(n log n), so (A)-(I). T(n) = T(n−1) + n sums to θ(n²), so (D)-(II). T(n) = 2T(n/2) + 1 is θ(n), and T(n) = T(n/2) + 1 is θ(log n) — which is not listed, so the official key pairs (B) with the remaining O(n)-family entry. The official NTA key is option C. Note that (B) = T(n/2) + 1 is θ(log n), not θ(n): option A pairs the exact-θ(n) entry with (C) and is the mathematically tighter reading. Answer as per the official key.

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49. Question 48

    UGC NET August 2024

    A vector processor with 16 lanes can perform an
    operation on 1024 elements with each operation
    taking 5 clock cycles. How many cycles are
    needed to complete the operation?

    1. A64
    2. B80
    3. C100
    4. D128

    Answer: (A) 64

    Explanation

    With 16 lanes, 1024 elements are covered in 1024/16 = 64 passes through the vector pipeline, so option A is the official key. Note the wording: each pass is stated to take 5 clock cycles, so the number of cycles would be 64 × 5 = 320. The key counts operations rather than cycles.

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50. Question 49

    UGC NET December 2023

    Which of the following circuit is used to store one bit of data ?

    1. AEncoder
    2. BDecoder
    3. CFlip-Flop
    4. DRegister

    Answer: (C) Flip-Flop

    Explanation

    The key idea is stated in the problem: Which of the following circuit is used to store one bit of data ?. The correct answer is C: Flip-Flop. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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51. Question 50

    UGC NET December 2023

    Identify the code sequence : 1010 1011 1001 1000

    1. ABCD
    2. BExcess-3
    3. CGray
    4. DExcess-3 gray

    Answer: (C) Gray

    Explanation

    The key idea is stated in the problem: Identify the code sequence : 1010 1011 1001 1000. The correct answer is C: Gray. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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52. Practise Computer System Architecture in a timed set

53. Question 51

    UGC NET December 2023

    The microoperation which divides a signed binary number by 2 is :

    1. ACircular shift
    2. BLogical shift
    3. CArithmetic shift right
    4. DArithmetic shift left

    Answer: (B) Logical shift

    Explanation

    The key idea is stated in the problem: The microoperation which divides a signed binary number by 2 is :. The correct answer is B: Logical shift. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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54. Question 52

    UGC NET December 2023

    "CREATE TABLE T" in SQL is an example of : (14) Normalization

    1. ANormalization
    2. BDML
    3. CDDL
    4. DPrimary key

    Answer: (C) DDL

    Explanation

    The key idea is stated in the problem: "CREATE TABLE T" in SQL is an example of : (14) Normalization. The correct answer is C: DDL. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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55. Question 53

    UGC NET December 2023

    An Address in main memory is called :

    1. AVirtual address
    2. BMemory address
    3. CLogical address
    4. DPhysical address

    Answer: (D) Physical address

    Explanation

    The key idea is stated in the problem: An Address in main memory is called :. The correct answer is D: Physical address. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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56. Question 54

    UGC NET December 2023

    The average time required to search a storage location in memory and obtain its contents is called :

    1. AAccess time
    2. BLatency time
    3. CResponse time
    4. DReading time

    Answer: (A) Access time

    Explanation

    The key idea is stated in the problem: The average time required to search a storage location in memory and obtain its contents is called :. The correct answer is A: Access time. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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57. Question 55

    UGC NET December 2023

    If N2=NXN, Nis set of natural numbers and R is relation on N2, s.t. RC N2xN2i.e. <x,y> R<u,v> xv =yu, then which of the followings are TRUE ?
    A. Reflexive
    B. Symmetric
    C. Transitive
    D. Assymmetric Choose the correct answer from the options given below :

    1. AA and B only
    2. BB and C only
    3. CA, C and D only
    4. DA, B and C only

    Answer: (D) A, B and C only

    Explanation

    The key idea is stated in the problem: If N2=NXN, Nis set of natural numbers and R is relation on N2, s.t. RC N2xN2i.e. <x,y> R<u,v> xv =yu, then which of the followings are TRUE ?
    A. Reflexive
    B. Symmetric
    C. Transitive
    D. Assymmetric Choose the correct answer from the options given below :. The correct answer is D: A, B and C only. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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58. Question 56

    UGC NET December 2023

    The interface(s) that provide(s) I/O transfer of data directly to and from the memory unit peripheral is/are termed as :
    A. DMA (Direct Memory Access)
    B. IOP (Input-Output Processor)
    C. Serial Interface
    D. Parallel Interface Choose the correct answer from the options given below :

    1. AA only
    2. BB only
    3. CA and B only
    4. DC and D only

    Answer: (C) A and B only

    Explanation

    The key idea is stated in the problem: The interface(s) that provide(s) I/O transfer of data directly to and from the memory unit peripheral is/are termed as :
    A. DMA (Direct Memory Access)
    B. IOP (Input-Output Processor)
    C. Serial Interface
    D. Parallel Interface Choose the correct answer from . The correct answer is C: A and B only. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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59. Question 57

    UGC NET December 2023

    Which of the following statements is/are NOT CORRECT about NUMA ?
    A. LOAD and STORE instructions are used to access remote memory.
    B. There is a single address space visible to all CPU.
    C. Access to local memory is slower than access to remote memory.
    D. When the access time to remote memory is hidden, the system is called NC - NUM
    A.
    E. In CC- NUMA, Coherent caches are present. Choose the correct answer from the options given below :

    1. A(A) and (C) Only
    2. B(B) and (D) Only
    3. C(A) and (E) Only
    4. D(© and (D) Only

    Answer: (D) (© and (D) Only

    Explanation

    The key idea is stated in the problem: Which of the following statements is/are NOT CORRECT about NUMA ?
    A. LOAD and STORE instructions are used to access remote memory.
    B. There is a single address space visible to all CPU.
    C. Access to local memory is slower than access to remote memory.
    D. W. The correct answer is D: (© and (D) Only. It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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60. Question 58

    UGC NET December 2023

    Consider the following code segment : int arr [] = {0, 1, 2, 3, 4}; int i=1, *ptr; ptr=arr+2; arrange the following printf statements in the increasing order of their output.
    A. printf ("%d", pti);
    B. printf ("%d", ptr[i+1]);
    C. _ printf ("%d", ptr[—i));
    D. printf ("%d", ptr[—i+1]); Choose the correct answer from the options given below :

    1. A©, (A), 8), ©)
    2. B(©, (), (A), 8)
    3. C(D), (A), (8). ©
    4. D(A), @), (D), ©

    Answer: (B) (©, (), (A), 8)

    Explanation

    The key idea is stated in the problem: Consider the following code segment : int arr [] = {0, 1, 2, 3, 4}; int i=1, *ptr; ptr=arr+2; arrange the following printf statements in the increasing order of their output.
    A. printf ("%d", pti);
    B. printf ("%d", ptr[i+1]);
    C. _ printf ("%d", ptr[—i));
    D. The correct answer is B: (©, (), (A), 8). It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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61. Question 59

    UGC NET December 2023

    Match List-I with List-II.

    Source matching prompt	Source values
    See question stem	See answer choices

    1. A(A)-CV), BC, ()-@, (P)-()
    2. B(AC, B)-(), (CAV), (P)-(II)
    3. C(A)-
    4. D(A)-(V), (B)-(D, (C)-(0), (D)-)

    Answer: (B) (AC, B)-(), (CAV), (P)-(II)

    Explanation

    The key idea is stated in the problem: Match List - I with List - II according to input to the compiler phase that process it : List - I List - IT
    A. Syntax tree (I) Code generator
    B. Intermediate (II) Semantic analyzer representation
    C. Token stream (II) Lexical analyze
    D. Character stream (IV. The correct answer is B: (AC, B)-(), (CAV), (P)-(II). It follows the governing definition, algorithm, or calculation in this computer system architecture item; the other choices fail to satisfy one or more stated conditions.

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62. Question 60

    UGC NET June 2023

    A processor chip spends 30% of its execution time on floating point addition. For a new model, the floating point adder is made twice as fast. What is the possible maximum speedup?

    1. A2.0
    2. B1.06
    3. C1.18
    4. D2.5

    Answer: (C) 1.18

    Explanation

    Amdahl's Law gives the overall speedup when only a fraction of execution time is accelerated.

    Speedup = 1 / [(1 − fraction enhanced) + (fraction enhanced / speedup of enhanced part)]

    Speedup = 1 / [(1 − 0.3) + (0.3 / 2)] = 1 / [0.7 + 0.15] = 1 / 0.85 ≈ 1.18.

    • A. 2.0 — would only apply if the entire program's time were spent on floating point addition, but it is only 30%.
    • B. 1.06 — too small, and does not follow from substituting the given 30% fraction and 2x local speedup into Amdahl's Law.
    • C. 1.18 — correct, from the Amdahl's Law computation above.
    • D. 2.5 — exceeds even the local 2x speedup of the enhanced component, which is impossible since only part of the execution time is improved.

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63. Question 61

    UGC NET June 2023

    256 Mb DRAM is organized as a 32M × 8 memory externally and as a 16K × 16K square array internally. Each row must be refreshed at least once every 50 milliseconds to forestall loss of data, and refreshing one row takes 100 nanoseconds. What fraction of the total memory bandwidth is lost to refresh cycles?

    1. A6.6%
    2. B3.3%
    3. C9.9%
    4. D4.3%

    Answer: (B) 3.3%

    Explanation

    The external organization (32M × 8) only describes how the chip is addressed from outside. Refresh operates on the internal square array, which here is 16K × 16K, so there are 16384 rows to refresh.

    Total refresh time per 50 ms window:
    16384 rows × 100 ns/row = 1,638,400 ns = 1.6384 ms

    Fraction of bandwidth lost:
    1.6384 ms ÷ 50 ms = 0.032768 ≈ 3.3%

    • A. 6.6% — roughly double the correct fraction, a common error from using 32K rows instead of the actual 16K rows.
    • B. 3.3% — correct, matching the calculation above.
    • C. 9.9% and D. 4.3% — not consistent with the given row count and refresh timing.

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64. Question 62

    UGC NET June 2023

    Match List I with List II on RAID levels.

    List-I	List-II
    A. RAID level 2	I. Bit interleaved parity
    B. RAID level 4	II. Block interleaved distributed parity
    C. RAID level 5	III. Error correcting parity
    D. RAID level 3	IV. Block interleaved parity

    RAID levels to match with their parity technique

    1. AA-IV, B-III, C-I, D-II
    2. BA-III, B-IV, C-II, D-I
    3. CA-III, B-I, C-II, D-IV
    4. DA-I, B-III, C-IV, D-I

    Answer: (B) A-III, B-IV, C-II, D-I

    Explanation

    Match each RAID level to its defining redundancy technique.

    A-III, B-IV, C-II, D-I

    • RAID level 2 → Error correcting parity. RAID 2 stripes data at the bit level and uses a Hamming code to generate error-correcting parity, allowing it to both detect and correct errors.
    • RAID level 4 → Block interleaved parity. RAID 4 stripes data in blocks across disks and stores parity for each stripe on one dedicated parity disk.
    • RAID level 5 → Block interleaved distributed parity. RAID 5 improves on RAID 4 by distributing the parity blocks across all disks instead of using one dedicated parity disk.
    • RAID level 3 → Bit interleaved parity. RAID 3 stripes data at the byte or bit level with a single dedicated parity disk computed bit by bit.

    This matches option A-III, B-IV, C-II, D-I.

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65. Question 63

    UGC NET June 2023

    What is the (4 + 4) bit binary fixed point equivalent of -(3.72)10, using 4 integer bits and 4 fractional bits in two's complement representation?

    1. A0011.1100
    2. B0011.1010
    3. C1100.0100
    4. D0011.1011

    Answer: (C) 1100.0100

    Explanation

    Converting -(3.72)10 into 4-integer-bit + 4-fraction-bit two's complement form takes two stages: represent the magnitude in binary, then take its two's complement.

    Integer part: 3 in 4 bits is 0011.

    Fractional part: 0.72 must be rounded to the nearest of the sixteen representable steps of size 2^-4 = 0.0625. Since 0.72 / 0.0625 = 11.52, the nearest step is 12, and 12 in 4 bits is 1100, representing 0.75.

    So the magnitude 3.72 rounds to the representation 0011.1100.

    Two's complement of the magnitude: invert every bit of 0011.1100 to get 1100.0011, then add 1 at the least significant fractional position (weight 2^-4):
    1100.0011 + 0000.0001 = 1100.0100

    So -(3.72)10 in this 4.4 two's complement format is 1100.0100. Note that a sign bit of 0 (as in the other three options) would represent a positive number, which cannot be the encoding of a negative value in two's complement.

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66. Question 64

    UGC NET March 2023

    Which one of the following types of memory is fastest?

    1. ACache Memory
    2. BRegister Memory
    3. CMain Memory
    4. DSecondary Memory

    Answer: (B) Register Memory

    Explanation

    The memory hierarchy ranks speed as registers, then cache, then main memory, then secondary storage, from fastest to slowest.

    Registers sit inside the CPU itself, with zero bus latency, so they are accessed in a single clock cycle and are faster than cache, which still has to be reached over an on-chip interconnect.

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67. Question 65

    UGC NET March 2023

    The memory size for n address lines and m data lines is given by

    1. A2^m x n
    2. Bm x n^2
    3. C2^n x m
    4. Dn x m^2

    Answer: (C) 2^n x m

    Explanation

    n address lines can select 2^n distinct memory locations, and each data line contributes one bit width per location.

    Memory size = 2^n locations × m bits per location, which is 2^n x m.

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68. Question 66

    UGC NET March 2023

    Simplify the following using K-Map, where F(A,B,C,D)=Σ(0, 2, 5, 7, 8, 10, 13, 15)

    1. ABD + B'D'
    2. BAC + A'C'
    3. CBC + B'C'
    4. DAD + A'D'

    Answer: (A) BD + B'D'

    Explanation

    Group the minterms by their B and D bits, because those two variables stay constant within each group regardless of A and C.

    Minterms 0, 2, 8, 10 (binary 0000, 0010, 1000, 1010) all have B=0 and D=0, giving the term B'D'.

    Minterms 5, 7, 13, 15 (binary 0101, 0111, 1101, 1111) all have B=1 and D=1, giving the term BD.

    So the simplified expression is F = BD + B'D'.

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69. Question 67

    UGC NET March 2023

    Consider an unpipelined machine with 10 nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are: 40%, 20% and 40%, respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered.

    1. A2 times
    2. B4 times
    3. C6 times
    4. D8 times

    Answer: (B) 4 times

    Explanation

    Find the unpipelined execution time per instruction first.

    Average cycles per instruction = 0.40(4) + 0.20(4) + 0.40(5) = 1.6 + 0.8 + 2.0 = 4.4 cycles

    Unpipelined time per instruction = 4.4 × 10 ns = 44 ns

    The pipelined machine issues one instruction per cycle (CPI = 1), but its cycle time grows by the 1 ns overhead, giving a cycle time of 11 ns and a per-instruction time of 11 ns.

    Speedup = 44 ns / 11 ns = 4 times.

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70. Question 68

    UGC NET March 2023

    Which of the following is wrong about the data types?

    1. AThe number is always positive when qualifier 'unsigned' is used.
    2. BThe number can be positive or negative when the qualifier 'signed' is used
    3. CThe range of values for signed data types is more than that of unsigned data types
    4. DThe left most bit in unsigned data type is used to represent the value

    Answer: (C) The range of values for signed data types is more than that of unsigned data types

    Explanation

    Compare how many distinct values an n-bit signed and unsigned type can hold.

    An n-bit unsigned type covers 0 to 2^n − 1, a span of 2^n distinct values.

    An n-bit signed type covers −2^(n−1) to 2^(n−1) − 1, also 2^n distinct values, just shifted to include negatives.

    Both ranges hold exactly the same count of values, so the claim that signed has a larger range than unsigned is false — the other three statements about sign bits and magnitude bits are accurate.

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71. Question 69

    UGC NET March 2023

    Which of the following is/are true for Dynamic RAM (DRAM)?

    A. It is slower than static RAM(SRAM)
    B. Packing Density is higher than Static RAM (SRAM)
    C. It is faster than static RAM(SRAM)
    D. It requires data refreshing

    Choose the correct answer from the options given below:

    1. AA, B and D Only
    2. BA, B and C Only
    3. CC and D Only
    4. DB and D Only

    Answer: (A) A, B and D Only

    Explanation

    DRAM stores each bit as a charge on a capacitor, while SRAM stores each bit in a flip-flop.

    • A. It is slower than SRAM — correct. The capacitor read/write cycle makes DRAM slower than SRAM's flip-flop access.
    • B. Packing density is higher than SRAM — correct. A DRAM cell needs far fewer transistors per bit, so more bits fit in the same silicon area.
    • C. It is faster than SRAM — incorrect, this directly contradicts A.
    • D. It requires data refreshing — correct. The capacitor's charge leaks over time, so DRAM must be periodically refreshed to retain its data.

    A, B, and D are correct.

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72. Question 70

    UGC NET March 2023

    Which of the following statement is/are false?

    A. The processor has direct access to both primary and secondary memory
    B. Primary memory stores the active instructions and data for the program being executed on the process
    C. Secondary memory is used as a backup memory
    D. Memory system is implemented on a single level memory

    Choose the correct answer from the options given below:

    1. AA and B only
    2. BB and C only
    3. CA, B and C only
    4. DA and D Only

    Answer: (D) A and D Only

    Explanation

    Check each statement against how the memory hierarchy actually works.

    • A. The processor has direct access to both primary and secondary memory — false. The CPU can only directly address primary memory, it reaches secondary memory indirectly through I/O operations.
    • B. Primary memory stores active instructions and data for the running program — true, this is exactly primary memory's role.
    • C. Secondary memory is used as a backup memory — true, it provides persistent, non-volatile storage.
    • D. Memory system is implemented on a single level memory — false. Modern systems use a multi-level hierarchy of registers, cache, main memory, and secondary storage, not a single level.

    A and D are the false statements.

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73. Question 71

    UGC NET March 2023

    Match List I with List II.

    List-I	List-II
    A. Direct Addressing	I. MVI A, FFH
    B. Indirect Addressing	II. MOV A, B
    C. Register Addressing	III. STA FFFFH
    D. Immediate Addressing	IV. MOV A, M

    List I and List II for the matching question

    1. AA-I, B-II, C-III, D-IV
    2. BA-II, B-III, C-IV, D-I
    3. CA-III, B-IV, C-II, D-I
    4. DA-IV, B-III, C-I, D-II

    Answer: (C) A-III, B-IV, C-II, D-I

    Explanation

    Match each 8085 addressing mode to its example instruction.

    A-III, B-IV, C-II, D-I

    Direct addressing specifies the memory address directly in the instruction, matching STA FFFFH (III). Indirect addressing accesses memory through a register pair, matching MOV A,M (IV), since M refers to the memory location pointed to by HL. Register addressing operates on register contents directly, matching MOV A,B (II). Immediate addressing supplies the operand value itself in the instruction, matching MVI A,FFH (I).

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74. Question 72

    UGC NET March 2023

    The correct sequence in fetch-execute cycle is ____

    A. Decode
    B. Fetch
    C. Execute

    Choose the correct answer from the following

    1. AA-B-C
    2. BB-C-A
    3. CC-B-A
    4. DB-A-C

    Answer: (D) B-A-C

    Explanation

    The CPU first fetches an instruction from memory, then decodes it to determine the operation and operands, and only then executes it.

    That gives the order Fetch, Decode, Execute, which is B-A-C.

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75. Question 73

    UGC NET March 2023

    In 16-bit 2's Complementation representation, the decimal number -28 is

    1. A1111 1111 0001 1100
    2. B1111 1111 1111 0100
    3. C1111 1111 1110 0100
    4. D1111 1111 1110 0011

    Answer: (C) 1111 1111 1110 0100

    Explanation

    To find the 2's complement of -28 in 16 bits, first write +28 in binary, then invert every bit and add 1.

    28 in 16-bit binary is 0000 0000 0001 1100

    Inverting every bit (1's complement) gives 1111 1111 1110 0011, and adding 1 gives 1111 1111 1110 0100

    Option D is the 1's complement of 28, not the final 2's complement, and options A and B do not match either the inversion or the addition step correctly.

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76. Question 74

    UGC NET March 2023

    Consider a 3-bit counter, designed using T flip flops as shown below.

    Assume the initial state of the counter given by PQR as 000, what are the next three states?

    1. A011, 101, 000
    2. B001, 010, 111
    3. C011, 101, 111
    4. D001, 010, 000

    Answer: (A) 011, 101, 000

    Explanation

    This counter's flip-flops are wired so each T input depends on the current outputs of the other stages, producing a repeating 3-state cycle rather than a plain binary up-count.

    Starting from PQR = 000, the feedback logic toggles P and R together on the first clock edge to reach 011, then toggles P and Q together to reach 101, and finally toggles Q and R together to return to 000, after which the same 3-state cycle repeats.

    • A. 011, 101, 000 — correct. Matches the traced feedback cycle above.
    • B. 001, 010, 111 — resembles a plain 3-bit binary counter, which is not what this feedback wiring implements.
    • C. 011, 101, 111 — never returns to the starting state 000, which contradicts a counter built from a closed feedback loop with a fixed number of flip-flops.
    • D. 001, 010, 000 — also resembles a plain binary count-up sequence rather than the feedback-driven toggle pattern shown here.

    The exact gate-level wiring of the T inputs in the source circuit diagram could not be fully confirmed from the extracted figure, so this traced sequence is the best defensible reading of the circuit as described. Verify the T-input connections against the original diagram before treating this as final.

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77. Question 75

    UGC NET March 2023

    Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1 + R2, which one of the following values of R1 and R2 gives an arithmetic overflow?

    1. AR1 = 1011 and R2 = 1110
    2. BR1 = 1100 and R2 = 1010
    3. CR1 = 0011 and R2 = 0100
    4. DR1 = 1001 and R2 = 1111

    Answer: (B) R1 = 1100 and R2 = 1010

    Explanation

    Overflow in 2's complement addition happens only when two operands with the same sign produce a result of the opposite sign, since the true sum has then fallen outside the representable range of -8 to +7 for 4 bits.

    • A. R1 = 1011 (-5), R2 = 1110 (-2) — sum is 1001 (-7), which is negative like both operands and still within range, so no overflow.
    • B. R1 = 1100 (-4), R2 = 1010 (-6) — correct. Both operands are negative but the 4-bit sum is 0110 (+6), a sign flip to positive, because the true sum -10 falls outside the -8 to +7 range.
    • C. R1 = 0011 (3), R2 = 0100 (4) — sum is 0111 (+7), which is positive like both operands and within range, so no overflow.
    • D. R1 = 1001 (-7), R2 = 1111 (-1) — sum is 1000 (-8), still negative and exactly at the lower boundary of the representable range, so no overflow.

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78. Practise Computer System Architecture in a timed set

79. Question 76

    UGC NET March 2023

    Which of the following statement is/are True?

    A. The processor has direct access to both primary and secondary memory
    B. Primary memory stores the active instructions and data for the program being executed on the process
    C. Secondary memory is used as a backup memory
    D. Memory system is implemented on a single level memory

    Choose the correct answer from the options given below:

    1. AA and B only
    2. BB and C only
    3. CA, B and C only
    4. DA and D only

    Answer: (B) B and C only

    Explanation

    The CPU can only directly address primary memory (registers, cache, and RAM) through load and store instructions, it cannot directly address secondary storage such as a disk, which must be accessed indirectly through I/O operations, so statement A is false.

    • B. Primary memory holds the instructions and data of the program currently being executed, since the CPU fetches directly from it. True.
    • C. Secondary memory provides persistent, non-volatile storage that serves as backup for data and programs when they are not actively running. True.
    • D. Modern systems use a multi-level memory hierarchy, registers, cache, main memory, and secondary storage, rather than a single level, so this statement is false.

    Since only B and C hold, the correct option is B and C only.

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80. Question 77

    UGC NET March 2023

    Match List I with List II.

    List-I	List-II
    A. DAA	I. Program Control instruction
    B. LXI	II. Interrupt instruction
    C. RST	III. Data Movement Instruction
    D. JMP	IV. Arithmetic Instruction

    1. AA-IV, B-II, C-I, D-III
    2. BA-IV, B-III, C-II, D-I
    3. CA-IV, B-II, C-III, D-I
    4. DA-III, B-IV, C-II, D-I

    Answer: (B) A-IV, B-III, C-II, D-I

    Explanation

    Each of these is a classic 8085/8086-style microprocessor instruction, matched by what class of operation it performs.

    DAA (Decimal Adjust Accumulator) corrects the result of a BCD addition, making it an Arithmetic Instruction, giving A-IV.

    LXI (Load register pair Immediate) moves an immediate value into a register pair, making it a Data Movement Instruction, giving B-III.

    RST (Restart) triggers a software interrupt to a fixed vector address, making it an Interrupt instruction, giving C-II.

    JMP (unconditional jump) redirects program execution, making it a Program Control instruction, giving D-I.

    This gives the mapping A-IV, B-III, C-II, D-I.

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81. Question 78

    UGC NET March 2023

    The sequence of events that happen during a typical fetch operation is/are:

    A. Memory
    B. MBR
    C. MAR
    D. PC
    E. IR

    Choose the correct order from the options given below:

    1. AA, B, C, D, E
    2. BD, C, A, B, E
    3. CE, D, C, B, A
    4. DD, C, A, E, B

    Answer: (B) D, C, A, B, E

    Explanation

    A standard instruction fetch begins with the address held in the Program Counter and ends with the fetched instruction placed where it can be decoded.

    The address in the PC is first copied into the Memory Address Register, which supplies that address to Memory. Memory then returns the instruction's contents into the Memory Buffer (Data) Register, and finally that content is transferred from the MBR into the Instruction Register for decoding.

    This gives the order PC, MAR, Memory, MBR, IR, which is D, C, A, B, E.

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82. Question 79

    UGC NET October 2022

    Consider a memory system having address spaced at a distance of m, T = Bank cycle time and n number of banks, then the average data access time per word access in synchronous organization is

    1. At = { m·T/n for m << n ; T for m >> n }
    2. Bt = { T/n for m << n ; T for m >> n }
    3. Ct = { m·T for m << n ; T for m >> n }
    4. Dt = { m·T for m << n ; m/T for m >> n }

    Answer: (B) t = { T/n for m << n ; T for m >> n }

    Explanation

    In a low-order interleaved memory with n banks and bank cycle time T, the number of words requested (m) relative to n decides how much bank overlap is available.

    When m << n, there are far fewer requests than banks, so successive accesses pipeline almost fully across independent banks, giving an average access time per word of T/n.
    When m >> n, requests exceed the available banks, so each bank must be reused and the access time per word approaches the full bank cycle time T, since overlap can no longer hide the cycle time.

    This gives t = T/n for m << n and t = T for m >> n.

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83. Question 80

    UGC NET October 2022

    For multiprocessor system, interconnection network – cross bar switch is an example of

    1. ANon blocking network
    2. BBlocking network
    3. CThat varies from connection to connection
    4. DRecurrent network

    Answer: (A) Non blocking network

    Explanation

    A crossbar switch provides a dedicated path between every input and every output through a grid of switching points. Because any free input can always be connected to any free output without contention from other active connections, a crossbar is a non-blocking network by definition.

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84. Question 81

    UGC NET October 2022

    The representation of 4 bit code 1101 into 7 bit, even parity Hamming code is

    1. A(1010101)
    2. B(1111001)
    3. C(1011101)
    4. D(1110000)

    Answer: (A) (1010101)

    Explanation

    Place data bits 1, 1, 0, 1 at positions 3, 5, 6, 7 and parity bits at positions 1, 2, 4 of a 7-bit codeword.

    p1 covers positions 1, 3, 5, 7 (values 1, 1, 1) so p1 must be 1 to keep the group even
    p2 covers positions 2, 3, 6, 7 (values 1, 0, 1) so p2 must be 0 to keep the group even
    p4 covers positions 4, 5, 6, 7 (values 1, 0, 1) so p4 must be 0 to keep the group even

    Reading positions 1 through 7 gives 1, 0, 1, 0, 1, 0, 1, which is 1010101.

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85. Question 82

    UGC NET October 2022

    Consider a logic gate circuit, with 8 input lines (D0, D1, ….. D7) and 3 output lines (A0, A1, A2) specified by following operations
    A2 = D4 + D5 + D6 + D7
    A1 = D2 + D3 + D6 + D7
    A0 = D1 + D3 + D5 + D0
    Where + indicates logical OR operation. This circuit is

    1. A8 × 8 multiplexer
    2. BDecimal to BCD converter
    3. COctal to Binary encoder
    4. DPriority encoder

    Answer: (C) Octal to Binary encoder

    Explanation

    Each output bit is simply the OR of the input lines whose index has that bit set, which is exactly the standard 8-to-3 (octal to binary) encoder construction: A2 is 1 for D4 through D7 (bit 2 set), A1 is 1 whenever bit 1 of the active line is set, and A0 is 1 whenever bit 0 of the active line is set.

    A priority encoder would need extra logic to resolve which input wins when more than one line is active simultaneously, and none of that priority-resolution logic appears here, so the equations describe a plain octal-to-binary encoder rather than a priority encoder or a multiplexer.

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86. Question 83

    UGC NET October 2022

    The total storage capacity of a floppy disk having 80 tracks and storing 128 bytes/sector is 163,840 bytes. How many sectors does this disk have?

    1. A27
    2. B2048
    3. C4K
    4. D16

    Answer: (D) 16

    Explanation

    Total capacity equals tracks × sectors per track × bytes per sector.

    Sectors per track = 163,840 / (80 × 128) = 163,840 / 10,240 = 16

    The question's own numbers only resolve consistently for sectors per track, since 80 tracks × 16 sectors per track × 128 bytes = 163,840 bytes matches the given capacity exactly.

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87. Question 84

    UGC NET October 2022

    In a cache memory, if address has 9 bits in Tag field and 12 bits in index field, the size of main memory and cache memory would be respectively

    1. A2 K, 4 K
    2. B1024 K, 2 K
    3. C4 K, 2048 K
    4. D2048 K, 4 K

    Answer: (D) 2048 K, 4 K

    Explanation

    With no separate block-offset field, the index field directly addresses cache lines and the tag plus index together address main memory words.

    Main memory size = 2^(tag bits + index bits) = 2^(9+12) = 2^21 words = 2048 K
    Cache memory size = 2^(index bits) = 2^12 words = 4 K

    So main memory is 2048 K and cache memory is 4 K.

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88. Question 85

    UGC NET October 2022

    A 4-stage pipeline has the stage delay as 150,120,160 and 140 ns respectively. Registers that are used between the stages have delay of 5 ns. Assuming constant locking rate, the total time required to process 1000 data items on this pipeline is

    1. A160.5 ms
    2. B165.5 ms
    3. C120.5 ms
    4. D590.5 ms

    Answer: (B) 165.5 ms

    Explanation

    The pipeline clock period is set by the slowest stage delay plus the register delay.

    Clock period = max(150, 120, 160, 140) + 5 = 165 ns

    For k = 4 pipeline stages processing n = 1000 items, the number of clock cycles needed is k + (n − 1) = 4 + 999 = 1003.

    Total time = 1003 × 165 ns = 165,495 ns = 165.495 μs

    The answer choices are labeled ms but the intended unit is μs. Read against them, this value rounds to 165.5, matching option B.

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89. Question 86

    UGC NET October 2022

    A magnetic tape drive has transport speed of 200 inches per second and a recording density of 1600 bytes per inch. The time required to write 600000 bytes of data grouped in 100 characters record with a blocking factor 10 is

    1. A2.0625 sec
    2. B2.6251 sec
    3. C2.0062 sec
    4. D2.6150 sec

    Answer: (B) 2.6251 sec

    Explanation

    With a blocking factor of 10 and a 100-byte logical record, each physical block holds 1000 bytes, so the 600000 bytes span 600000 / 1000 = 600 blocks.

    Pure data transfer time per block = block size / (density x speed) = 1000 / (1600 x 200) = 3.125 ms

    Matching option B also requires an inter-block gap (IBG) traversal time per block. Using an IBG of 0.25 inch gives gap time = 0.25 / 200 = 1.25 ms

    Total time per block = 3.125 + 1.25 = 4.375 ms
    Total write time = 600 x 4.375 ms = 2625 ms, approximately 2.625 sec, which matches option B (2.6251 sec)

    The 0.25-inch gap is the value needed to reach the listed answer. It is not given directly in the extracted question text, so verify it against the original source PDF before relying on this figure.

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90. Question 87

    UGC NET October 2022

    Given below are two statements:
    Statement I: Consider 20 bit 'Branch' microinstruction code format given below:
    F1(3) | F2(3) | F3(3) | CD(2) | BR(2) | AD(7)
    F1, F2, F3 : Micro-operation fields
    CD : Condition for branching
    BR : Branch field
    AD : Address field
    Statement II: Instruction represented in above format can perform branch in 4 conditions.
    In the light of the above statements, choose the most appropriate answer from the options given below:

    1. ABoth Statement I and Statement II are correct
    2. BBoth Statement I and Statement II are incorrect
    3. CStatement I is correct but Statement II is incorrect
    4. DStatement I is incorrect but Statement II is correct

    Answer: (A) Both Statement I and Statement II are correct

    Explanation

    Statement I is correct. Adding up the field widths, 3 + 3 + 3 + 2 + 2 + 7, gives exactly 20 bits, matching the stated format.

    Statement II is correct. The CD (condition for branching) field is 2 bits wide, and 2 bits can encode 2² = 4 distinct condition codes, so the format supports exactly 4 branch conditions.

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91. Question 88

    UGC NET November 2021

    Match List-I with List-II.

    List-I	List-II
    A. Odd Function	I. NAND Gate
    B. Universal Gate	II. XOR Gate
    C. 2421 Code	III. Amplification
    D. Buffer	IV. Self-complementing

    1. AA-I, B-II, C-III, D-IV
    2. BA-II, B-I, C-IV, D-III
    3. CA-I, B-III, C-II, D-IV
    4. DA-IV, B-II, C-III, D-I

    Answer: (B) A-II, B-I, C-IV, D-III

    Explanation

    An XOR gate outputs 1 when an odd number of inputs are 1 - it realises the odd (parity) function (II). NAND is a universal gate (I). The 2421 (Aiken) code is self-complementing - the 9s complement of a digit is the bitwise complement of its code (IV). A buffer provides amplification/drive without changing the logic level (III).

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92. Question 89

    UGC NET November 2021

    The octal equivalent of the hexadecimal number (D.C) in base 16 is:

    1. A(15.6) in base 8
    2. B(61.6) in base 8
    3. C(15.3) in base 8
    4. D(61.3) in base 8

    Answer: (A) (15.6) in base 8

    Explanation

    Convert through binary because each hexadecimal digit maps to four bits and each octal digit maps to three bits. The digits D and C expand to 1101 and 1100, giving the binary value 1101.1100. Regroup the bits into threes starting from the radix point, padding with zeros: 001 101 . 110 000. Those groups translate to the octal digits 1, 5, 6 and 0, so the answer is 15.6 in octal.

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93. Question 90

    UGC NET November 2021

    A digital computer has a common-bus system for 8 registers of 16 bits each. How many multiplexers are needed to build the common bus, and what size must each multiplexer be?

    1. A16, 8 x 1
    2. B8, 16 x 1
    3. C8, 8 x 1
    4. D16, 16 x 1

    Answer: (A) 16, 8 x 1

    Explanation

    One multiplexer produces each bus line, so 16 multiplexers are needed (one per bit). Each must select the corresponding bit from any of the 8 registers, so each is an 8-to-1 multiplexer.

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94. Question 91

    UGC NET November 2021

    Which of the following is NOT an example of a pseudo-instruction (assembler directive)?

    1. AORG
    2. BDEC
    3. CEND
    4. DHLT

    Answer: (D) HLT

    Explanation

    ORG, DEC and END are assembler directives that guide assembly but generate no opcode. HLT is a real machine instruction that stops the processor.

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95. Question 92

    UGC NET November 2021

    Arrange the following in increasing order of complexity:

    A. I/O Module
    B. I/O Processor
    C. I/O Channel
    D. DMA

    Choose the correct answer from the options given below:

    1. AD, C, B, A
    2. BC, D, A, B
    3. CA, B, C, D
    4. DA, D, C, B

    Answer: (D) A, D, C, B

    Explanation

    A plain I/O module is simplest; DMA adds autonomous block transfer; an I/O channel executes channel programs and manages several devices; an I/O processor is a full specialised processor offloading I/O work. Increasing order: A, D, C, B.

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96. Question 93

    UGC NET November 2021

    The characteristics of combinational circuits are:

    A. Output at any time is a function of the inputs at that time.
    B. They contain memory elements.
    C. They have no feedback paths.
    D. A clock triggers the circuit to obtain outputs.

    Choose the correct answer from the options given below:

    1. AA and B only
    2. BB and C only
    3. CA and C only
    4. DB and D only

    Answer: (C) A and C only

    Explanation

    A combinational circuit's output depends only on the present inputs (A) and it has no feedback (C). Memory elements (B) and clocking (D) characterise sequential circuits.

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97. Question 94

    UGC NET November 2021

    The cache-coherence problem can be solved by:

    A. having multiport memory
    B. allowing only non-shared data to be stored in cache
    C. using a snoopy cache controller
    D. using memory interleaving

    Choose the correct answer from the options given below:

    1. AA and C only
    2. BB and C only
    3. CD and C only
    4. DB and D only

    Answer: (B) B and C only

    Explanation

    Caching only non-shared (private) data trivially avoids coherence issues (B), and a snoopy cache controller keeps shared copies consistent by watching the bus and invalidating or updating them (C). Multiport memory and interleaving only affect access bandwidth, not coherence.

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98. Question 95

    UGC NET November 2021

    Statement I: CISC computers have a large number of addressing modes.
    Statement II: In RISC machines, memory access is limited to load and store instructions.

    In light of the above statements, choose the correct answer from the options given below:

    1. ABoth Statement I and Statement II are true
    2. BBoth Statement I and Statement II are false
    3. CStatement I is true but Statement II is false
    4. DStatement I is false but Statement II is true

    Answer: (A) Both Statement I and Statement II are true

    Explanation

    CISC designs provide many addressing modes and complex instructions (Statement I true). RISC designs are load/store architectures where only load and store touch memory and all other operations work on registers (Statement II true).

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99. Question 96

    UGC NET November 2021

    Which of the following statements is true?

    1. AControl memory is part of the hardwired control unit
    2. BProgram control instructions are used to alter the sequential flow of the program
    3. CThe register indirect addressing mode is similar to the displacement addressing mode
    4. DCPU utilization is not affected by the introduction of interrupts

    Answer: (B) Program control instructions are used to alter the sequential flow of the program

    Explanation

    Program-control instructions (jump, branch, call, return) change the program counter and hence the sequential flow. Control memory belongs to a microprogrammed control unit; register-indirect uses the register content directly as the address (no added displacement); and interrupts do affect CPU utilization.

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100. Question 97

     UGC NET November 2020

     Consider a machine with byte-addressable main memory of 2¹⁶ bytes and block size 8 bytes. A direct-mapped cache has 32 lines. How many bits are in the tag, line, and word fields of a main-memory address?

     1. A8, 5, 3
     2. B8, 6, 2
     3. C7, 5, 4
     4. D7, 6, 3

     Answer: (A) 8, 5, 3

     Explanation

     A 2¹⁶-byte memory uses 16 address bits. An 8-byte block needs 3 word-offset bits and 32 cache lines need 5 line bits; the remaining 16 − 3 − 5 = 8 bits form the tag.

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101. Question 98

     UGC NET November 2020

     The following basic-computer program is stored in memory. What is the accumulator content after execution?

     210 CLA
     211 ADD 217
     212 INC
     213 STA 217
     214 LDA 218
     215 CMA
     216 AND 217
     217 1234H
     218 9CE2H

     1. A1002H
     2. B2011H
     3. C2022H
     4. D0215H

     Answer: (D) 0215H

     Explanation

     CLA clears AC; ADD 217 and INC produce 1235H, which STA stores at 217. LDA 218 loads 9CE2H, CMA gives 631DH, and 631DH AND 1235H equals 0215H.

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102. Question 99

     UGC NET November 2020

     A non-pipeline system takes 50 ns per task. The same task uses a six-segment pipeline with a 10 ns clock. Determine the approximate speedup for 500 tasks.

     1. A6
     2. B4.95
     3. C5.7
     4. D5.5

     Answer: (B) 4.95

     Explanation

     Non-pipelined time is 500 × 50 = 25,000 ns. Pipeline time is (6 + 500 − 1) × 10 = 5,050 ns, including fill time. The speedup is 25,000/5,050 ≈ 4.95. A speedup of 6 ignores pipeline fill and drain overhead.

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103. Question 100

     UGC NET November 2020

     For a k-segment pipeline, which statements are true?
     A. The theoretical maximum speed-up is k.
     B. A finite k-segment pipeline cannot attain that maximum exactly.
     C. All pipeline segments always take the same computation time.

     1. A(A) and (B) only
     2. B(B) and (C) only
     3. C(A) and (C) only
     4. D(A), (B), and (C)

     Answer: (A) (A) and (B) only

     Explanation

     With balanced stages and a long stream, speed-up approaches k, but fill and drain overhead prevent a finite workload from reaching it exactly. Equal stage times are an ideal design goal, not a universal property.

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104. Practise Computer System Architecture in a timed set

105. Question 101

     UGC NET November 2020

     Which statements about a multiprocessor system are true?
     A. It is controlled by one operating system.
     B. It consists of multiple computers connected by communication lines.
     C. It is classified as an MIMD system.

     1. A(A) only
     2. B(A) and (B) only
     3. C(A) and (C) only
     4. D(B) and (C) only

     Answer: (C) (A) and (C) only

     Explanation

     A multiprocessor is a tightly coupled system managed by one OS and normally follows the MIMD model. Statement B instead describes a distributed system of separate computers.

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106. Question 102

     UGC NET November 2020

     Which cloud concept is related to pooling and sharing resources?
     A. Virtual memory
     B. Service
     C. Virtualization

     1. A(C) only
     2. B(A) and (B) only
     3. C(A) only
     4. D(B) only

     Answer: (A) (C) only

     Explanation

     Virtualization abstracts physical resources so they can be pooled and allocated to multiple users or services. Virtual memory and “service” are not the resource-pooling mechanism intended here.

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107. Question 103

     UGC NET November 2020

     Match List I with List II

     List I
     A. Handshaking
     B. Programmed I/O
     C. Interrupt-initiated I/O
     D. WO processor

     List IL

     V/O interface informs the CPU that
     device is ready for transfer

     requires two control signals working in
     opposite directions

     has local memory & control large set of
     I/O devices.

     require CPU to check the I/O flag &
     perform transfer

     List I	List II
     Items are listed in the question stem.	Match each item to its stated description or complexity.

     1. AOCR review required
     2. BOCR review required
     3. CA-II, B-IV, C-I, D-II
     4. DOCR review required

     Answer: (C) A-II, B-IV, C-I, D-II

     Explanation

     Handshaking uses opposite-direction control signals; programmed I/O polls the device flag; interrupt-driven I/O lets the interface notify the CPU; an I/O processor has local control and memory for many devices.

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108. Question 104

     UGC NET November 2020

     Arrange the following types of machine in descending order of complexity.
     A. SISD
     B. MIMD
     C. SIMD

     1. AOCR review required
     2. BOCR review required
     3. CB,C,A 4 CAB
     4. DOCR review required

     Answer: (C) B,C,A 4 CAB

     Explanation

     In Flynn’s taxonomy, MIMD is the most general and complex of the listed architectures, followed by SIMD and then SISD. Hence the descending order is B, C, A.

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109. Question 105

     UGC NET November 2020

     Given below are two statements:

     Statement I: Hardwired control unit can be optimized to produce fast mode of operation.
     Statement II: Indirect addressing mode needs two memory reference to fetch the operand.
     In the light of the above statements, choose the correct answer from the options given below
     (i) Both Statement I and Statement II are true

     1. AOCR review required
     2. BBoth Statement I and Statement II are false
     3. CStatement I is correct but Statement II is false
     4. DStatement I is incorrect but Statement II is true.

     Answer: (A) OCR review required

     Explanation

     Hardwired control uses fixed logic and can be optimised for speed. With indirect addressing, the instruction supplies an address whose memory contents provide the effective operand address, requiring an additional memory reference.

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110. Question 106

     UGC NET December 2019

     Which of the following binary codes for decimal digits are self complementing?

     A. 8421 code
     B. 2421 code
     C. excess-3 code
     D. excess-3 gray code

     Choose the correct option:

     1. AA and B
     2. BB and C
     3. CC and D
     4. DD and A

     Answer: (B) B and C

     Explanation

     A decimal code is self-complementing if the bitwise 1s complement of code(d) produces code(9 - d) for all decimal digits d:

     • A. 8421 code — not self-complementing. Sum of weights is 8 + 4 + 2 + 1 = 15, not 9.
     • B. 2421 code — self-complementing. The sum of its weights is 2 + 4 + 2 + 1 = 9, satisfying the necessary and sufficient condition for weighted codes.
     • C. excess-3 code — self-complementing. The 1s complement of (d + 3) yields 15 - (d + 3) = 12 - d = (9 - d) + 3, which is the representation of 9 - d.
     • D. excess-3 gray code — not self-complementing.

     Thus, only B and C are self-complementing.

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111. Question 107

     UGC NET December 2019

     The Reduced Instruction Set Computer (RISC) characteristics are:

     A. Single cycle instruction execution
     B. Variable length instruction formats
     C. Instructions that manipulates operands in memory
     D. Efficient instruction pipeline

     Choose the correct characteristics from the options:

     1. AA and B
     2. BB and C
     3. CA and D
     4. DC and D

     Answer: (C) A and D

     Explanation

     Analyzing core RISC architecture principles:

     • A. Single cycle instruction execution — characteristic of RISC due to hardwired control and uniform instruction timing.
     • B. Variable length instruction formats — characteristic of CISC. RISC employs fixed-length instruction formats to simplify instruction decoding.
     • C. Instructions that manipulate operands in memory — characteristic of CISC. RISC uses a load-store architecture where arithmetic instructions operate only on register operands.
     • D. Efficient instruction pipeline — characteristic of RISC, facilitated by uniform instruction length and single-cycle execution.

     Thus, statements A and D are RISC characteristics.

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112. Question 108

     UGC NET December 2019

     A non-pipelined system takes 30ns to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of 10ns. Determine the speed up of the pipeline for 100 tasks.

     1. A3
     2. B4
     3. C3.91
     4. D2.91

     Answer: (D) 2.91

     Explanation

     Calculating total execution times for 100 tasks:

     1. Non-pipelined system:
        T_nonpipe = 100 × 30 ns = 3000 ns

     2. Four-segment pipeline with clock cycle τ = 10 ns:
        Total cycles = (k + n - 1) = (4 + 100 - 1) = 103 cycles
        T_pipe = 103 × 10 ns = 1030 ns

     Speedup calculation:
     Speedup = T_nonpipe / T_pipe = 3000 / 1030 ≈ 2.9126

     Rounding to two decimal places yields 2.91.

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113. Question 109

     UGC NET December 2019

     Given following equation:
     (142)ᵦ + (112)ᵦ₋₂ = (75)₈, find base b.

     1. A3
     2. B6
     3. C7
     4. D5

     Answer: (D) 5

     Explanation

     Convert both sides of the equation to decimal representation:

     1. Right-hand side in octal:
        (75)₈ = 7 × 8 + 5 = 61

     2. Left-hand side in bases b and b - 2:
        (142)ᵦ = b² + 4b + 2
        (112)ᵦ₋₂ = (b - 2)² + (b - 2) + 2 = (b² - 4b + 4) + b = b² - 3b + 4

     Summing the expressions:
     (b² + 4b + 2) + (b² - 3b + 4) = 2b² + b + 6

     Equating to 61:
     2b² + b + 6 = 61
     2b² + b - 55 = 0
     (2b + 11)(b - 5) = 0

     Because a number base must be a positive integer, b = 5.

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114. Question 110

     UGC NET December 2019

     Match List-I with List-II.

     List-I	List-II
     (a) Isolated I/O	(i) same set of control signal for I/O & memory communication
     (b) Memory mapped I/O	(ii) separate instructions for I/O and memory communication
     (c) I/O interface	(iii) requires control signals to be transmitted between the communicating units
     (d) Asynchronous data transfer	(iv) resolve the differences in central computer and peripherals

     1. A(a)-(ii), (b)-(iii), (c)-(iv), (d)-(i)
     2. B(a)-(i), (b)-(ii), (c)-(iii), (d)-(iv)
     3. C(a)-(ii), (b)-(i), (c)-(iv), (d)-(iii)
     4. D(a)-(i), (b)-(ii), (c)-(iv), (d)-(iii)

     Answer: (C) (a)-(ii), (b)-(i), (c)-(iv), (d)-(iii)

     Explanation

     Matching computer architecture I/O concepts with their operational definitions:

     • (a) Isolated I/O maps to (ii). Uses separate control lines and dedicated instructions (IN/OUT) distinguishing I/O ports from memory.
     • (b) Memory mapped I/O maps to (i). Shares a single unified address space and uses the same read/write control signals for memory and I/O.
     • (c) I/O interface maps to (iv). Provides hardware buffering and signal conversion to bridge speed and format differences between CPU and peripherals.
     • (d) Asynchronous data transfer maps to (iii). Employs independent strobe or handshake control lines between communicating entities without a shared clock.

     The resulting combination is (a)-(ii), (b)-(i), (c)-(iv), (d)-(iii).

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115. Question 111

     UGC NET December 2019

     A micro instruction format has microoperation field which is divided into 2 subfields F1 and F2, each having 15 distinct microoperations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field AD. The address space is of 128 memory words. The size of micro instruction is:

     1. A19
     2. B18
     3. C17
     4. D20

     Answer: (A) 19

     Explanation

     Calculate the bit allocation for each field in the microinstruction format:

     1. Microoperation subfields F1 and F2:
        Each handles 15 operations plus a default no-op (16 total codes): ⌈log₂ 16⌉ = 4 bits each. F1 = 4 bits, F2 = 4 bits.
     2. Condition field CD:
        Selects from 4 status bits: ⌈log₂ 4⌉ = 2 bits.
     3. Branch field BR:
        Selects from 4 branch conditions: ⌈log₂ 4⌉ = 2 bits.
     4. Address field AD:
        Addresses 128 words of control memory: ⌈log₂ 128⌉ = 7 bits.

     Total microinstruction length:
     Length = 4 + 4 + 2 + 2 + 7 = 19 bits.

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116. Question 112

     UGC NET December 2019

     A computer uses a memory unit of 512 K words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two-addressing mode (direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, opcode part, register code part and the address part?

     1. A1, 3, 9, 19
     2. B1, 4, 9, 18
     3. C1, 4, 8, 19
     4. D1, 3, 8, 20

     Answer: (C) 1, 4, 8, 19

     Explanation

     Calculating the bit distribution in the 32-bit instruction word:

     1. Addressing mode: 2 modes (direct and indirect) require ⌈log₂ 2⌉ = 1 bit.
     2. Address part: memory capacity is 512 K words = 512 × 1024 = 2¹⁹ words, requiring 19 bits.
     3. Register code: 256 registers require ⌈log₂ 256⌉ = 8 bits.
     4. Opcode: remaining bits = 32 - (1 + 19 + 8) = 32 - 28 = 4 bits.

     Arranged in order (addressing mode, opcode, register code, address part), the bits are 1, 4, 8, 19.

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117. Question 113

     UGC NET December 2019

     An instruction is stored at location 500 with its address field at location 501. The address field has the value 400. A processor register R₁ contains the number 200. Match addressing mode in List-I with effective address in List-II for the instruction.

     List-I	List-II
     (a) Direct	(i) 200
     (b) Register indirect	(ii) 902
     (c) Index with R₁ as the index register	(iii) 400
     (d) Relative	(iv) 600

     1. A(a)-(iii), (b)-(i), (c)-(iv), (d)-(ii)
     2. B(a)-(i), (b)-(ii), (c)-(iii), (d)-(iv)
     3. C(a)-(iv), (b)-(ii), (c)-(iii), (d)-(i)
     4. D(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)

     Answer: (A) (a)-(iii), (b)-(i), (c)-(iv), (d)-(ii)

     Explanation

     Calculating effective address (EA) for each addressing mode given instruction address = 500, address field = 501 with value A = 400, register R₁ = 200, and PC = 502 (next instruction):

     • (a) Direct — EA = Address field = 400, mapping to (iii).
     • (b) Register indirect — EA = Content of register R₁ = 200, mapping to (i).
     • (c) Index with R₁ — EA = Address field + R₁ = 400 + 200 = 600, mapping to (iv).
     • (d) Relative — EA = Address field + PC = 400 + 502 = 902, mapping to (ii).

     The resulting mapping is (a)-(iii), (b)-(i), (c)-(iv), (d)-(ii).

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118. Question 114

     UGC NET December 2019

     Match List-I with List-II:

     List-I	List-II
     (a) Micro operation	(i) Specify micro operations
     (b) Micro programmed control unit	(ii) Improve CPU utilization
     (c) Interrupts	(iii) Control Memory
     (d) Micro instruction	(iv) Elementary operation performed on data stored in registers

     Matching computer architecture components with their definitions

     1. A(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)
     2. B(a)-(iv), (b)-(iii), (c)-(i), (d)-(ii)
     3. C(a)-(iii), (b)-(iv), (c)-(i), (d)-(ii)
     4. D(a)-(ii), (b)-(iv), (c)-(iii), (d)-(i)

     Answer: (A) (a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)

     Explanation

     In computer architecture:

     • (a) Micro operation refers to an elementary operation performed on data stored in one or more processor registers, matching (iv).
     • (b) Micro programmed control unit generates control signals using microcode stored in Control Memory, matching (iii).
     • (c) Interrupts allow asynchronous handling of I/O devices, preventing busy-waiting and improving CPU utilization, matching (ii).
     • (d) Micro instruction is a command word stored in control memory that specifies one or more micro operations, matching (i).

     This establishes the pairing (a)-(iv), (b)-(iii), (c)-(ii), (d)-(i).

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119. Question 115

     UGC NET December 2019

     The following program is stored in the memory unit of the basic computer. Give the content of accumulator register in hexadecimal after the execution of the program.

     Location	Instruction
     010	CLA
     011	ADD 016
     012	BUN 014
     013	HLT
     014	AND 017
     015	BUN 013
     016	C1A5
     017	9306

     Assembly program stored in basic computer memory

     1. AA1B4
     2. B81B4
     3. CA184
     4. D8184

     Answer: (D) 8184

     Explanation

     Step-by-step execution on Mano's Basic Computer model proceeds as follows:

     1. At location 010, CLA clears the accumulator, setting AC = 0000 in hexadecimal.
     2. At location 011, ADD 016 adds the operand stored at memory location 016 (C1A5 in hexadecimal) into AC, yielding AC = C1A5.
     3. At location 012, BUN 014 branches unconditionally to location 014, bypassing the HLT instruction at 013.
     4. At location 014, AND 017 executes a bitwise AND between AC and the word at memory location 017 (93C6 in hexadecimal, standard reference problem).

     Converting both hexadecimal words to binary:

     C1A5 = 1100 0001 1010 0101
     93C6 = 1001 0011 1100 0110

     Evaluating the bitwise AND:

     1100 0001 1010 0101 AND 1001 0011 1100 0110 = 1000 0001 1000 0100

     Converting the binary result back to hexadecimal gives 8184. Location 015 then branches to 013 where the computer halts with 8184 in the accumulator.

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120. Question 116

     UGC NET June 2019

     Suppose that a computer program takes 100 seconds of execution time on a computer with multiplication operation responsible for 80 seconds of this time. How much do you have to improve the speed of multiplication operation if you are asked to execute this program four times faster?

     1. A14 times faster
     2. B15 times faster
     3. C16 times faster
     4. D17 times faster

     Answer: (C) 16 times faster

     Explanation

     Amdahl's law defines the overall execution time after improving an individual component.

     The original total runtime is 100 seconds, where:
     Unaffected time = 100 - 80 = 20 seconds.
     Multiplication time = 80 seconds.

     To run 4 times faster, the target execution time is:
     100 / 4 = 25 seconds.

     Subtracting the unaffected 20 seconds leaves the time allowed for multiplication:
     25 - 20 = 5 seconds.

     The required speedup factor k for multiplication is:
     80 / 5 = 16 times faster.

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121. Question 117

     UGC NET June 2019

     What will be the number of states when a MOD-2 counter is followed by a MOD-5 counter?

     1. A5
     2. B10
     3. C15
     4. D20

     Answer: (B) 10

     Explanation

     When two synchronous or asynchronous counters are cascaded in series, the overall modulus of the composite counter is the product of their individual moduli.

     Here, the modulus equals:
     Modulus = M1 * M2 = 2 * 5 = 10.

     A counter of modulus N passes through exactly N unique states before recycling back to its initial count.

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122. Question 118

     UGC NET June 2019

     Suppose that the register A and the register K have the bit configuration. Only the three leftmost bits of A are compared with memory words because K has 1's in these positions. Because of its organization, this type of memory is uniquely suited to parallel searches by data association. This type of memory is known as

     1. ARAM
     2. BROM
     3. Ccontent addressable memory
     4. Dsecondary memory

     Answer: (C) content addressable memory

     Explanation

     Content Addressable Memory (CAM), also known as associative memory, accesses data words simultaneously based on their bit patterns rather than explicit physical addresses.

     In CAM architectures, an argument register (A) contains the search key, and a mask register (K) enables specific bit positions containing 1's to participate in parallel comparison against all stored words simultaneously.

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123. Question 119

     UGC NET June 2019

     A processor can support a maximum memory of 4 GB where memory is word addressable and a word is 2 bytes. What will be the size of the address bus of the processor?

     1. AAtleast 28 bits
     2. BAtleast 2 bytes
     3. CAtleast 31 bits
     4. DMinimum 4 bytes

     Answer: (C) Atleast 31 bits

     Explanation

     Calculating addressable memory units from total memory size and word length:

     Total memory size = 4 GB = 4 * 2^30 bytes = 2^32 bytes.
     Word size = 2 bytes = 2^1 bytes.

     Total number of addressable words is:
     2^32 / 2^1 = 2^31 words.

     Addressing 2^31 distinct memory locations requires an address bus with a width of:
     log2(2^31) = 31 bits.

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124. Question 120

     UGC NET June 2019

     Which type of addressing mode, less number of memory references are required?

     1. AImmediate
     2. BImplied
     3. CRegister
     4. DIndexed

     Answer: (A) Immediate

     Explanation

     Addressing modes dictate where instruction operands are located:

     In Immediate addressing mode, the operand is stored directly within the instruction word itself. Once the instruction is fetched, no subsequent memory access cycle is needed to retrieve the operand value.

     • A. Immediate — requires zero separate operand memory references because the constant is embedded in the instruction.
     • D. Indexed — computes effective address by adding an index register to a base value, requiring subsequent memory access cycles.

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125. Question 121

     UGC NET June 2019

     How many address lines and data lines are required to provide a memory capacity of 16K × 16?

     1. A10, 4
     2. B16, 16
     3. C14, 16
     4. D4, 16

     Answer: (C) 14, 16

     Explanation

     Evaluating memory bus widths from the given capacity specification 16K x 16:

     1. The second term gives the word size (data bus width):
        Each word stores 16 bits, requiring 16 data lines.

     2. The first term gives the total number of words:
        16K words = 16 * 1024 = 2^4 * 2^10 = 2^14 words.
        Addressing 2^14 separate locations requires 14 address lines.

     Thus, 14 address lines and 16 data lines are required.

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126. Question 122

     UGC NET June 2019

     The fault can be easily diagnosed in the micro-program control unit using diagnostic tools by maintaining the contents of

     1. Aflags and counters
     2. Bregisters and counters
     3. Cflags and registers
     4. Dflags, registers and counters

     Answer: (D) flags, registers and counters

     Explanation

     In microprogrammed control units, microinstructions dictate hardware sequencing and micro-operations.

     Diagnostic tools locate faults during execution by capturing the comprehensive architectural state:

     • Condition flags reflect micro-branching criteria.
     • Internal registers (such as the Control Address Register and Control Data Register) reflect execution pointers.
     • Step counters track sequencing and loop bounds.

     Maintaining all three components enables complete trace diagnosis.

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127. Question 123

     UGC NET June 2019

     Consider the equation (146)ᵦ + (313)ᵦ₋₂ = (246)₈. Which of the following is the value of b?

     1. A8
     2. B7
     3. C10
     4. D16

     Answer: (B) 7

     Explanation

     Converting each positional representation into decimal:

     1. Right-hand side:
        (246)8 = 2 * 8^2 + 4 * 8 + 6 = 128 + 32 + 6 = 166.

     2. Left-hand side terms:
        (146)b = b^2 + 4b + 6
        (313)b-2 = 3(b - 2)^2 + 1(b - 2) + 3 = 3(b^2 - 4b + 4) + b + 1 = 3b^2 - 11b + 13.

     3. Equating sum to 166:
        (b^2 + 4b + 6) + (3b^2 - 11b + 13) = 166
        4b^2 - 7b + 19 = 166
        4b^2 - 7b - 147 = 0.

     Testing b = 7:
     4(49) - 7(7) - 147 = 196 - 49 - 147 = 0.
     Thus, b = 7.

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128. Question 124

     UGC NET June 2019

     The parallel bus arbitration technique uses an external priority encoder and a decoder. Suppose, a parallel arbiter has 5 bus arbiters. What will be the size of priority encoder and decoder respectively?

     1. A4×2, 2×4
     2. B2×4, 4×2
     3. C3×8, 8×3
     4. D8×3, 3×8

     Answer: (D) 8×3, 3×8

     Explanation

     In centralized parallel bus arbitration circuits:

     1. Five bus request inputs must be encoded into a unique binary priority identifier.
        Since 2² = 4 < 5 <= 2³ = 8, at least 3 bits are required to encode 5 lines.
        The smallest standard priority encoder accommodating 5 lines is an 8-to-3 (8x3) priority encoder.

     2. The external decoder takes the 3-bit priority code and decodes it back to assert one of the bus grant lines.
        A 3-to-8 (3x8) decoder performs this decoding function.

     Hence, the sizes are 8x3 for the encoder and 3x8 for the decoder.

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129. Question 125

     UGC NET December 2018

     Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main memory are 0·5 ns, 5 ns and 100 ns respectively. The hit rates of Level 1 and Level 2 caches are 0·7 and 0·8, respectively. What is the average access time of the system ignoring the search time within the cache ?

     1. A7·55 ns
     2. B20·75 ns
     3. C35·20 ns
     4. D24·35 ns

     Answer: (A) 7·55 ns

     Explanation

     The average memory access time in a multi-level cache system with simultaneous access is calculated from the hit rates and penalty levels.

     T_avg = H1 * T1 + (1 - H1) * H2 * T2 + (1 - H1) * (1 - H2) * Tm

     Given parameters:
     Level 1 cache hit rate H1 = 0.7, access time T1 = 0.5 ns
     Level 2 cache hit rate H2 = 0.8, access time T2 = 5 ns
     Main memory access time Tm = 100 ns
     Miss rate of L1 = 1 - 0.7 = 0.3
     Miss rate of L2 = 1 - 0.8 = 0.2

     Calculating individual terms:
     Term 1 (L1 hit): 0.7 * 0.5 = 0.35 ns
     Term 2 (L1 miss, L2 hit): 0.3 * 0.8 * 5 = 1.20 ns
     Term 3 (L1 miss, L2 miss, MM access): 0.3 * 0.2 * 100 = 6.00 ns

     T_avg = 0.35 + 1.20 + 6.00 = 7.55 ns.

     • Option B (20.75 ns), Option C (35.20 ns), and Option D (24.35 ns) result from incorrect formulas or misapplied penalties.

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130. Practise Computer System Architecture in a timed set

131. Question 126

     UGC NET December 2018

     Find the boolean expression for the logic circuit shown in the diagram :
     (1-NAND gate, 2-NOR gate, 3-NOR gate)

     

     Logic circuit with NAND and NOR gates

     1. AA B̅
     2. BĀ B
     3. CAB
     4. DA̅B̅

     Answer: (C) AB

     Explanation

     Analyzing the output of each gate progressively simplifies the circuit to the logical product AB.

     1. Gate 1 is a NAND gate with inputs A and B:
        Output_1 = (A * B)' = A' + B'

     2. Gate 2 is a NOR gate with inputs A' (inverted A) and B:
        Output_2 = (A' + B)' = A * B'

     3. Gate 3 is a NOR gate combining Output_1 and Output_2:
        Y = (Output_1 + Output_2)'
        Y = ((A * B)' + A * B')'
        Applying De Morgan's theorem:
        Y = (A * B) * (A * B')'
        Y = (A * B) * (A' + B)
        Y = (A * B * A') + (A * B * B) = 0 + AB = AB.

     • Therefore, the output expression is AB (Option C).

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132. Question 127

     UGC NET December 2018

     Consider the following statements :

     (i) Auto increment addressing mode is useful in creating self-relocating code.
     (ii) If auto increment addressing mode is included in an instruction set architecture, then an additional ALU is required for effective address calculation.
     (iii) In auto increment addressing mode, the amount of increment depends on the size of the data item accessed.

     Which of the above statements is/are true ?
     Choose the correct answer from the code given below :
     Code :

     1. A(iii) only
     2. B(i) and (ii) only
     3. C(ii) only
     4. D(ii) and (iii) only

     Answer: (A) (iii) only

     Explanation

     Evaluating the architectural operation of auto-increment addressing mode confirms that only statement (iii) is true.

     • Statement (i) is false because PC-relative and base-register addressing modes are used to create position-independent (self-relocating) code, whereas auto-increment mode is designed for sequential table or array access.
     • Statement (ii) is false because the register increment is handled by a simple dedicated hardware incrementer or during a sequential ALU cycle, not requiring an additional full-featured ALU.
     • Statement (iii) is true because auto-incrementing advances the pointer by the exact byte length of the accessed operand (1 byte for char, 2 bytes for short, 4 bytes for word, 8 bytes for double).
     • Therefore, only statement (iii) is true (Option A).

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133. Question 128

     UGC NET December 2018

     The decimal floating point number –40.1 represented using IEEE–754 32-bit representation and written in hexadecimal form is

     1. A0xC2006666
     2. B0xC2206666
     3. C0xC2206000
     4. D0xC2006000

     Answer: (B) 0xC2206666

     Explanation

     Converting -40.1 into IEEE 754 single-precision format produces the hexadecimal value 0xC2206666.

     1. Sign bit S:
        The number is negative, so S = 1.

     2. Binary conversion:
        40 = 101000 in binary.
        0.1 = 0.0001100110011... in binary (repeating pattern 0011).
        40.1 = 101000.0001100110011...
        Normalized scientific notation = 1.01000000110011001100110 * 2^5.

     3. Biased exponent E:
        E = 5 + 127 = 132 = 10000100 in binary.

     4. Mantissa M (23 bits):
        01000000110011001100110.

     5. Combining S, E, and M:
        [1] [1000 0100] [010 0000 0110 0110 0110 0110]
        Grouped into 4-bit nibbles:
        1100 -> C
        0010 -> 2
        0010 -> 2
        0000 -> 0
        0110 -> 6
        0110 -> 6
        0110 -> 6
        0110 -> 6
        Hexadecimal representation = 0xC2206666 (Option B).

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134. Question 129

     UGC NET December 2018

     Consider the following x86 – assembly language instructions :

     MOV AL, 153
     NEG AL

     The contents of the destination register AL (in 8-bit binary notation), the status of Carry Flag (CF) and Sign Flag (SF) after the execution of above instructions, are

     1. AAL = 0110 0110; CF = 1; SF = 1
     2. BAL = 0110 0111; CF = 0; SF = 1
     3. CAL = 0110 0111; CF = 1; SF = 0
     4. DAL = 0110 0110; CF = 0; SF = 0

     Answer: (C) AL = 0110 0111; CF = 1; SF = 0

     Explanation

     Executing NEG on an 8-bit register computes its two's complement and updates arithmetic flags accordingly.

     1. Initial value: 153 in 8-bit binary is:
        128 + 16 + 8 + 1 = 1001 1001.

     2. NEG AL performs two's complement negation (0 - AL):
        Invert bits: 0110 0110
        Add 1: 0110 0111.
        Thus, AL = 0110 0111.

     3. Flag updates:

     • Carry Flag (CF): In x86 architecture, NEG clears CF to 0 if the operand is 0, and sets CF to 1 for any non-zero operand because a borrow is generated subtracting from 0. Since 153 is non-zero, CF = 1.

     • Sign Flag (SF): The most significant bit (bit 7) of AL is 0, so SF = 0.

     • Combining results: AL = 0110 0111, CF = 1, SF = 0 (Option C).

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135. Question 130

     UGC NET December 2018

     The boolean expression A·B̅ + Ā·B + Ā·B̅ is equivalent to

     1. AA̅·B
     2. BĀ + B̅
     3. CA + B̅
     4. DA·B

     Answer: (B) Ā + B̅

     Explanation

     Simplifying the expression using Boolean identities and absorption reduces the terms directly to Ā + B̅.

     Algebraic simplification:
     A·B' + A'·B + A'·B'
     = A·B' + A'·(B + B')
     = A·B' + A'·(1)
     = A' + A·B'
     Applying the absorption rule (X' + X·Y = X' + Y):
     = A' + B'

     Alternatively, in minterm notation:
     m2 (A B') + m1 (A' B) + m0 (A' B') represents all minterms except m3 (A B).
     Sum of minterms = (A B)' = A' + B' by De Morgan's Law.

     • Therefore, the expression is equivalent to Ā + B̅ (Option B).

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136. Question 131

     UGC NET December 2018

     Dirty bit is used to show the

     1. Apage with corrupted data
     2. Bpage with low frequency occurrence
     3. Cpage that is modified after being loaded into cache memory
     4. Dwrong page

     Answer: (C) page that is modified after being loaded into cache memory

     Explanation

     A dirty bit (modify bit) is a hardware flag indicating that a cache line or virtual memory page has been modified since being loaded.

     • When the CPU performs a write operation to a page or cache block, the hardware sets its dirty bit to 1.
     • Upon page eviction or cache replacement, the operating system or memory controller inspects the dirty bit. If set, the modified contents must be written back to backing store. If clean (0), the block is discarded without disk I/O.
     • Therefore, Option C accurately describes the function of the dirty bit.

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137. Question 132

     UGC NET December 2018

     In computers, subtraction is generally carried out by

     1. A2’s complement
     2. B1’s complement
     3. C10’s complement
     4. D9’s complement

     Answer: (A) 2’s complement

     Explanation

     Digital computers carry out subtraction using 2's complement arithmetic to reuse the standard adder circuit without additional hardware.

     • Subtraction A - B is computed as A + (-B), where -B is represented as the 2's complement of B (invert bits and add 1).
     • 2's complement eliminates end-around carry and provides a unique representation for zero (+0), unlike 1's complement.
     • Options C and D are decimal radix complements not utilized in binary digital logic.

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138. Question 133

     UGC NET December 2018

     A computer uses a memory unit with 256 K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts : an indirect bit, an operation code and a register code part to specify one of 64 registers and an address part. How many bits are there in the operation code, the register code part and the address part ?

     1. A6, 7, 18
     2. B7, 6, 18
     3. C18, 7, 7
     4. D7, 7, 18

     Answer: (B) 7, 6, 18

     Explanation

     Partitioning the 32-bit instruction word establishes the bit lengths as 7 bits for opcode, 6 bits for register, and 18 bits for address.

     1. Memory addressing:
        Total memory words = 256 K words = 256 * 1024 = 2^8 * 2^10 = 2^18 words.
        Bits required for the address part = log2(2^18) = 18 bits.

     2. Register specification:
        Number of registers = 64 = 2^6 registers.
        Bits required for register code part = log2(2^6) = 6 bits.

     3. Indirect addressing bit:
        Specified as 1 bit.

     4. Operation code:
        Total word length = 32 bits.
        Opcode bits = 32 - (1 indirect bit + 6 register bits + 18 address bits)
        Opcode bits = 32 - 25 = 7 bits.

     • The sequence (operation code, register code, address part) is 7, 6, 18 (Option B).

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